IDT82P20516 2009 Integrated Device Technology, Inc. DSC-7266/- 16-Channel Short Haul E1 Line Inter- face Unit IDT and the " />
參數(shù)資料
型號(hào): IDT82P20516DBFG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 94/115頁(yè)
文件大小: 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝: 84
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.89W
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 484-LFBGA
供應(yīng)商設(shè)備封裝: 484-CABGA(19x19)
包裝: 托盤(pán)
包括: AIS 警報(bào)檢測(cè)器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測(cè)器,遠(yuǎn)程檢測(cè)器和發(fā)生器
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December 17, 2009
IDT82P20516
2009 Integrated Device Technology, Inc.
DSC-7266/-
16-Channel
Short Haul E1 Line Inter-
face Unit
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FEATURES
Integrates 16 channels E1 short haul line interface units for 120
E1 twisted pair cable and 75 E1 coaxial cable applications
Per-channel configurable Line Interface options
Fully integrated and software selectable receive and transmit
termination
Option 1: Fully Internal Impedance Matching with integrated receive
termination resistor
Option 2: Partially Internal Impedance Matching with common external
resistor for improved device power dissipation
Option 3: External impedance Matching termination
Supports global configuration and per-channel configuration to
E1 mode
Per-channel programmable features
Provides E1 short haul waveform templates and user-
programmable arbitrary waveform templates
Provides two JAs (Jitter Attenuator) for each channel of receiver
and transmitter
Supports AMI/HDB3 (for E1) encoding and decoding
Per-channel System Interface options
Supports Single Rail, Dual Rail with clock or without clock and
sliced system interface
Integrated Clock Recovery for the transmit interface to recover
transmit clock from system transmit data
Per-channel system and diagnostic functions
Provides transmit driver over-current detection and protection
with optional automatic high impedance of transmit interface
Detects and generates PRBS (Pseudo Random Bit Sequence),
ARB (Arbitrary Pattern) and IB (Inband Loopback) in either
receive or transmit direction
Provides defect and alarm detection in both receive and transmit
directions.
Defects include BPV (Bipolar Violation) /CV (Code Violation) and EXZ
(Excessive Zeroes)
Alarms include LLOS (Line LOS), SLOS (System LOS), TLOS
(Transmit LOS) and AIS (Alarm Indication Signal)
Programmable LLOS detection /clear levels. Compliant with ITU
and ANSI specifications
Various pattern, defect and alarm reporting options
Serial hardware LLOS reporting (LLOS, LLOS0) for all 16 channels
Register access to individual registers or 16-bit error counters
Supports Analog Loopback, Digital Loopback and Remote
Loopback
Supports line monitor
Hitless Protection Switching (HPS) without external Relays
Supports 1+1 and 1:1 hitless protection switching
Asynchronous hardware control (OE, RIM) for fast global high
impedance of receiver and transmitter (hot switching between
working and backup board)
High impedance transmitter and receiver while powered down
Per-channel register control for high impedance, independent for
receiver and transmitter
Clock Inputs and Outputs
Flexible master clock (N x 1.544 MHz or N x 2.048 MHz) (1
≤ N ≤
8, N is an integer number)
Integrated clock synthesizer can multiply or divide the reference
clock to a wide range of frequencies: 8 KHz, 64 KHz, 2.048 MHz,
4.096 MHz, 8.192 MHz, 19.44 MHz and 32.768 MHz
Microprocessor Interface
Supports Serial microprocessor interface
Other Key Features
IEEE1149.1 JTAG boundary scan
Two general purpose I/O pins
3.3 V I/O with 5 V tolerant inputs
3.3 V and 1.8 V power supply
Package: 484-pin Fine Pitch BGA (19 mm X 19 mm)
Applicable Standards
Bellcore TR-TSY-000009, GR-253-CORE and GR-499-CORE
ETSI CTR12/13
ETS 300166 and ETS 300 233
G.703, G.735, G.736, G.742, G.772, G.775, G.783 and G.823
O.161
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