參數(shù)資料
型號(hào)： IDT82P20516DBFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 81/115頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.89W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報(bào)檢測(cè)器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測(cè)器，遠(yuǎn)程檢測(cè)器和發(fā)生器
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Programming Information
68
December 17, 2009
AWG0 - Arbitrary Waveform Generation Control Register 0
AWG1 - Arbitrary Waveform Generation Control Register 1
Address: 008H, 048H, 088H, 0C8H, 108H, 148H, 188H, 1C8H, (CH1~CH8)
208H, 248H, 288H, 2C8H, 308H, 348H, 388H, (CH9~CH15)
7C8H (CH0)
Type: Read / Write
Default Value: 00H
Bit
Name
Description
7-
Reserved.
6
DONE
This bit is valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...) are set
to ‘1XXX’). This bit determines whether to enable the data writing/reading from RAM.
0: Disable. (default)
1: Enable.
5
RW
This bit is valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...) are set
to ‘1XXX’). This bit determines read/write direction.
0: Write data to RAM. (default)
1: Read data from RAM.
4 - 0
SAMP[4:0]
These bits are valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...)
are set to ‘1XXX’). These bits specify the RAM sample address.
00000: The RAM sample address is 0. (default)
00001: The RAM sample address is 1.
00010: The RAM sample address is 2.
......
10001: The RAM sample address is 17.
10010: The RAM sample address is 18.
10011 ~ 11111: The RAM sample address is 19.
Address: 009H, 049H, 089H, 0C9H, 109H, 149H, 189H, 1C9H, (CH1~CH8)
209H, 249H, 289H, 2C9H, 309H, 349H, 389H, (CH9~CH15)
7C9H (CH0)
Type: Read / Write
Default Value: 00H
Bit
Name
Description
7-
Reserved.
6 - 0
WDAT[6:0]
These bits are valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...)
are set to ‘1XXX’).
These bits contain the template sample data to be stored in RAM which address is specified by the SAMP[4:0] bits (b4~0,
AWG0,...). They are not updated until new template sample data is written.
7654
321
0
-
DONE
RW
SAMP4
SAMP3
SAMP2
SAMP1
SAMP0
765
43
21
0
-
WDAT6
WDAT5
WDAT4
WDAT3
WDAT2
WDAT1
WDAT0
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參數(shù)描述
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