參數(shù)資料
型號(hào)： IDT82P20516DBFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 24/115頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝： 84
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 16
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.89W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-LFBGA
供應(yīng)商設(shè)備封裝： 484-CABGA（19x19）
包裝： 托盤
包括： AIS 警報(bào)檢測(cè)器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測(cè)器，遠(yuǎn)程檢測(cè)器和發(fā)生器
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Pin Description
16
December 17, 2009
Common Control
VCOM[0]
VCOM[1]
Output
M20
M19
VCOM: Voltage Common Mode [1:0]
These pins are used only when the receive line interface is in Receive Differential mode and
connected without a transformer (transformer-less).
To enable these pins, the VCOMEN pin must be connected high. Refer to Figure-6 for the
connection.
When these pins are not used, they should be left open.
VCOMEN
Input
(Pull-Down)
L19
VCOMEN: Voltage Common Mode Enable
This pin should be connected high only when the receive line interface is in Receive Differen-
tial mode and connected without a transformer (transformer-less).
When not used, this pin should be left open.
REF
-
L20
REF: Reference Resistor
An external resistor (10 K
, ±1%) is used to connect this pin to ground to provide a standard
reference current for internal circuit. This resistor is required to ensure correct device opera-
tion.
RIM
Input
(Pull-Down)
AB11
RIM: Receive Impedance Matching
In Receive Differential mode, when RIM is low, all 16 receivers become High-Z and only exter-
nal impedance matching is supported. In this case, the per-channel impedance matching con-
figuration bits - the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...) - are
ignored.
In Receive Differential mode, when RIM is high, impedance matching is configured on a per-
channel basis by the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...).
This pin can be used to control the receive impedance state for Hitless Protection applica-
In Receive Single Ended mode, this pin should be left open.
OE
Input
V11
OE: Output Enable
OE enables or disables all Line Drivers globally.
A high level on this pin enables all Line Drivers while a low level on this pin places all Line
Drivers in High-Z state and independent from related register settings.
Note that the functionality of the internal circuit is not affected by OE.
If this pin is not used, it should be tied to VDDIO.
This pin can be used to control the transmit impedance state for Hitless protection applica-
TEHWE
Input
(Pull-Up)
V12
TEHWE: Hardware E1 Mode Selection Enable
When this pin is open, the E1 operation mode is selected by TEHW globally.
When this pin is low, the E1 operation mode is selected by the E1 bit (b0, CHCF,...) on a per-
channel basis.
TEHW
Input
(Pull-Up)
AB10
TEHW: Hardware E1 Mode Selection
When TEHWE is open, this pin selects the E1 operation mode globally:
Low - E1 mode;
When TEHWE is low, the input on this pin is ignored.
GPIO[0]
GPIO[1]
Output / Input
V10
AA10
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO)
respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
RST
Input
AA11
RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 s max-
imum. Refer to Section 4.1 Reset for an overview on reset options.
Name
I / O
Pin No.
Description
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