參數(shù)資料
型號(hào): IDT82P20516DBFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 23/115頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝: 84
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.89W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-LFBGA
供應(yīng)商設(shè)備封裝: 484-CABGA(19x19)
包裝: 托盤
包括: AIS 警報(bào)檢測(cè)器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測(cè)器,遠(yuǎn)程檢測(cè)器和發(fā)生器
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Pin Description
15
December 17, 2009
Clock
MCLK
Input
AB18
MCLK: Master Clock Input
MCLK provides a stable reference timing for the IDT82P20516. MCLK should be a clock with
+/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK is informed to the device by
MCKSEL[3:0].
If MCLK misses (duty cycle is less than 30% for 10 s) and then recovers, the device will be
reset automatically.
MCKSEL[0]
MCKSEL[1]
MCKSEL[2]
MCKSEL[3]
Input
AB17
W16
AA15
V15
MCKSEL[3:0]: Master Clock Selection
These four pins inform the device of the clock frequency input on MCLK:
CLKE1
Output
AB16
CLKE1: 8 KHz / E1 Clock Output
The output on CLKE1 can be enabled or disabled, as determined by the CLKE1_EN bit (b3,
When the output is enabled, CLKE1 outputs an 8 KHz or 2.048 MHz clock, as selected by the
CLKE1 bit (b2, CLKG). The output is locked to MCLK.
When the output is disabled, CLKE1 is in High-Z state.
CLKA
Input
AA14
CLKA: External E1 Clock Input A
External E1 (2.048 MHz) clock is input on this pin.
When not used, this pin should be connected to GNDD.
CLKB
Input
V14
CLKB: External E1 Clock Input B
External E1 (2.048 MHz) clock is input on this pin.
When not used, this pin should be connected to GNDD.
Name
I / O
Pin No.
Description
MCKSEL[3:0]*
Frequency (MHz)
0000
1.544
0001
1.544 X 2
0010
1.544 X 3
0011
1.544 X 4
0100
1.544 X 5
0101
1.544 X 6
0110
1.544 X 7
0111
1.544 X 8
1000
2.048
1001
2.048 X 2
1010
2.048 X 3
1011
2.048 X 4
1100
2.048 X 5
1101
2.048 X 6
1110
2.048 X 7
1111
2.048 X 8
Note:
0: GNDD
1: VDDIO
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