參數(shù)資料
型號(hào): IDT82P20516DBFG
廠(chǎng)商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 47/115頁(yè)
文件大小: 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標(biāo)準(zhǔn)包裝: 84
功能: 線(xiàn)路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.89W
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 484-LFBGA
供應(yīng)商設(shè)備封裝: 484-CABGA(19x19)
包裝: 托盤(pán)
包括: AIS 警報(bào)檢測(cè)器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測(cè)器,遠(yuǎn)程檢測(cè)器和發(fā)生器
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)當(dāng)前第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Functional Description
37
December 17, 2009
3.5.5.2 Pattern Detection
Data received from the line side or data input from the transmit
system side may be extracted for pattern detection. The direction of data
extraction is determined by the PD_POS bit (b3, PD,...). One of PRBS or
ARB pattern is selected for detection and IB detection is always active.
If data is extracted from the receive path, before pattern detection the
data should be decoded by using AMI or HDB3 (for E1). The decoding
rule is selected by the R_CODE bit (b2, RCF1,...).
If data is extracted from the transmit path, before pattern detection
the data should be decoded by using AMI or HDB3 (for E1) in Transmit
Dual Rail NRZ Format mode and Transmit Dual Rail RZ Format mode.
The decoding rule is selected by the T_CODE bit (b2, TCF1,...).
Pseudo Random Bit Sequence (PRBS) /Arbitrary Pattern (ARB)
Detection
The extracted data can be optionally inverted by the PAD_INV bit
(b2, PD,...) before PRBS/ARB detection.
The extracted data is used to compare with the desired pattern. The
desired pattern is re-generated from the extracted data if the desired
pattern is (2^20 - 1) QRSS per O.150-4.5, (2^15 - 1) PRBS per O.152 or
(2^11 - 1) PRBS per O.150; or the desired pattern is programmed in the
ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) if the desired pattern is
ARB. The desired pattern is selected by the PAD_SEL[1:0] bits (b1~0,
PD,...).
In summary, do the followings step by step to detect PRBS/ARB:
Select the detection direction by the PD_POS bit (b3, PD,...);
Set the ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) if the ARB
pattern is desired - this step is omitted if the PRBS pattern is
desired;
Select the desired PRBS/ARB pattern by the PAD_SEL[1:0] bits
(b1~0, PD,...).
The priority of decoding, data inversion, pattern re-generation, bit
programming and pattern comparison is shown in Figure-19.
Figure-19 PRBS / ARB Detection
During comparison, if the extracted data coincides with the re-gener-
ated PRBS pattern or the programmed ARB pattern for more than 64-bit
hopping window, the pattern is synchronized and the PA_S bit (b5,
STAT1,...) will be set.
In synchronization state, if more than 6 PRBS/ARB errors are
detected in a 64-bit hopping window, the pattern is out of synchroniza-
tion and the PA_S bit (b5, STAT1,...) will be cleared.
In synchronization state, each mismatched bit will generate a PRBS/
ARB error. When a PRBS/ARB error is detected during the synchroniza-
tion, the ERR_IS bit (b1, INTS2,...) will be set and an interrupt will be
reported by INT if not masked by the ERR_IM bit (b1, INTM2,...). The
PRBS/ARB error may be counted by an internal Error Counter. Refer to
A transition from ‘0’ to ‘1’ on the PA_S bit (b5, STAT1,...) or any tran-
sition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the PA_S bit (b5, STAT1,...) will
set the PA_IS bit (b5, INTS1,...) to ‘1’, as selected by the PA_IES bit (b5,
INTES,...). When the PA_IS bit (b5, INTS1,...) is ‘1’, an interrupt will be
reported by INT if not masked by the PA_IM bit (b5, INTM1,...).
from Rx path
or Tx path
Decoding
Data
Inversion
PRBS Re-
Generation
Comparison
ARB[23:0]
Programming
相關(guān)PDF資料
PDF描述
IDT82P2281PF TXRX T1/E1/J1 LONG/SHORT 80-TQFP
IDT82P2282PF TXRX T1/J1/E1 2CHAN 100-TQFP
IDT82P2284BB TXRX T1/J1/E1 4CHAN 208-PBGA
IDT82P2288BBG TXRX OCTAL T1/E1/J1 256-PBGA
IDT82P2521BHG IC LIU E1 21+1CH SHORT 640-PBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82P20516DBFG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA
IDT82P20516DBFGBLANK 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit
IDT82P2281 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:Single T1/E1/J1 Long Haul Short Haul Transceiver
IDT82P2281_09 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:Single T1/E1/J1 Long Haul / Short Haul Transceiver
IDT82P2281PF 功能描述:TXRX T1/E1/J1 LONG/SHORT 80-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器,接收器,收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)