
IDT82P20416
16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description
17
December 17, 2009
GPIO[0]
GPIO[1]
Output / Input
V10
AA10
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0,
GPIO)respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2,
GPIO)respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2,
GPIO)respectively.
RST
Input
AA11
RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 s max-
MCU Interface
INT
Output
AB13
INT: Interrupt Request
This pin indicates interrupt requests for all unmasked interrupt sources.
The output characteristics (open drain or push-pull internally) and the active level are deter-
mined by the INT_PIN[1:0] bits (b3~2,
GCF).CS
Input
V13
CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface.
A transition from high to low must occur on this pin for each Read/Write operation and CS
should remain low until the operation is over.
SCLK
Input
AB12
SCLK: Shift Clock
In Serial microprocessor interface, this multiplex pin is used as SCLK.
SCLK inputs the shift clock for the Serial microprocessor interface. Data on SDI is sampled by
the device on the rising edge of SCLK. Data on SDO is updated on the falling edge of SCLK.
SDI
Input
W13
SDI: Serial Data Input
In Serial microprocessor interface, this multiplex pin is used as SDI.
Address and data on this pin are serially clocked into the device on the rising edge of SCLK.
SDO
Output
AA12
SDO: Serial Data Output
In Serial microprocessor interface, this multiplex pin is used as SDO.
Data on this pin is serially clocked out of the device on the falling edge of SCLK.
JTAG (per IEEE 1149.1)
TRST
Input
Pull-Down
AB8
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS
Input
Pull-up
W11
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK
Input
W12
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
Name
I / O
Pin No.
Description