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參數(shù)資料
| 型號： | IDT821068PX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編解碼器 |
| 英文描述： | OCTAL PROGRAMMABLE PCM CODEC |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 28/45頁 |
| 文件大小： | 589K |
| 代理商： | IDT821068PX |
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INDUSTRIAL TEMPERATURE RANGE
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
28
b7
R
/W
SL[7]
b6
0
b5
1
b4
1
b3
0
b2
1
b1
1
b0
0
Command
I/O data
SL[6]
SL[5]
SL[4]
SL[3]
SL[2]
SL[1]
SL[0]
b7
R
/W
R
b6
0
TOI
b5
1
TF
b4
1
LMO
b3
0
L/C
b2
0
b1
1
b0
1
Command
I/O data
CS[2]
CS[1]
CS[0]
19. Level Meter Channel Select, Level Meter Mode Select, Level Meter On/off, Teletax Pulse Frequency and Dual Tone Output In-
vert (33H/B3H), Read/Write
Level Meter Channel Select bits (CS[2:0]) select the channel, data on which will be level metered.
CS = 000: Channel 1 is selected (default);
CS = 001: Channel 2 is selected;
CS = 010: Channel 3 is selected;
CS = 011: Channel 4 is selected;
CS = 100: Channel 5 is selected;
CS = 101: Channel 6 is selected;
CS = 110: Channel 7 is selected;
CS = 111: Channel 8 is selected.
Level Meter Mode Select bit (L/C) determines the mode of level meter operation.
L/C = 0: Message mode is selected. Compressed PCM will be output to LMRH transparently (default);
L/C = 1: Meter mode is selected. Linear PCM data will be metered and output to LMRH and LMRL, when data_ready bit in LMRL
register is ‘1’.
Level Meter On/off bit (LMO) enables the level meter.
LMO = 0: Level meter is disabled (default);
LMO = 1: Level meter is enabled.
Teletax Pulse Frequency bit (TF) selects the frequency of teletax pulse.
TF = 0: Teletax pulse frequency is 16 kHz (default);
TF = 1: Teletax pulse frequency is 12 kHz.
Dual Tone Output Invert bit (TOI) determines whether output tone signal will be inverted or not.
TOI = 0: no inversion (default);
TOI = 1: output signal is inverted.
20. FSK Flag Length (34H/B4H), Read/Write
Flag Length bits (FL[7:0]) determine the number of flag bits ‘1’ which will be transmitted between the transmission of message bytes. The
value is valid from 0 to 255(d). The default value is 0(d). If 0(d) is selected, no flag signal will be sent.
21. FSK Data Length (35H/B5H), Read/Write
Data Length bits (WL[7:0]) determine the number of all the data bytes which will be transmitted except flag. The value is valid from 0 to 64(d).
Any value larger than 64(d) will be taken as 64(d) by the CPU.
The default value of this register is 0(d). When 0(d) is selected, none of the word data will be sent out. When Mark After Send (MAS bit in
Global Command 24) is set to ‘1’, the mark signal will be sent; while Mark After Send is set to ‘0’, the transmission of mark signal will be termi-
nated.
22. FSK Seizure Length (36H/B6H), Read/Write
Seizure Length bits (SL[7:0]) determine the number of ‘01’ pairs which represent seizure phase (Seizure Length is two times of the value in
SL[7:0], which is valid from 0 to 255(d), corresponding to Seizure Length 0 to 510). The default value is 0(d). When 0(d) is selected, no seizure
signal will be sent.
b7
R
/W
FL[7]
b6
0
b5
1
b4
1
b3
0
b2
1
b1
0
b0
0
Command
I/O data
FL[6]
FL[5]
FL[4]
FL[3]
FL[2]
FL[1]
FL[0]
b7
R
/W
WL[7]
b6
0
b5
1
b4
1
b3
0
b2
0
b1
0
b0
1
Command
I/O data
WL[6]
WL[5]
WL[4]
WL[3]
WL[2]
WL[1]
WL[0]
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