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| 型號(hào)： | IDT821068PX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編解碼器 |
| 英文描述： | OCTAL PROGRAMMABLE PCM CODEC |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 20/45頁 |
| 文件大?。?/td> | 589K |
| 代理商： | IDT821068PX |
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INDUSTRIAL TEMPERATURE RANGE
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
20
Address Specified by Local
Command
b4 b3 b2 b1 b0
X X X 1 1
(b1b0 = 11, 4 bytes DATA)
In/Out Data
Registers being
R
/W
Byte 1
Byte 2
Byte 3
Byte 4
X X X 11
X X X 10
X X X 01
X X X 00
X X X 1 0
(b1b0 = 10, 3 bytes DATA)
Byte 1
Byte 2
Byte 3
X X X 10
X X X 01
X X X 00
X X X 0 1
(b1b0 = 01, 2 bytes DATA)
Byte 1
Byte 2
X X X 01
X X X 00
X X X 0 0
(b1b0 = 00, 1 byte DATA)
Byte 1
X X X 00
In GCI mode, both the location of time slot (determined by S1 and
S0 pin) and the b4 bit in Program Start Byte would indicate which
channel to be addressed.
The b[4:0] of a Local Command determine which one of the 12
Local Registers will be addressed for the configured channel.
IDT821068 provides a Consecutive Adjacent Addressing for Read/
Write Local Registers. If the address for Local Register is specified in a
Local Command, then, according to the value of ‘b1b0’ of the address,
there will be 1 to 4 adjacent local registers will be read/write
automatically with the highest order first. For example, if the address
of the register specified by the Local Command is end with ‘11’ (b1b0
= ‘11’), 4 adjacent registers will be Read/Write by this Command. If
b1b0 = ‘10’, then 3 adjacent registers will be Read/Write. If b1b0 = ‘01’,
then only 2 adjacent registers will be Read/Write. If b1b0 = ‘00’, then
only this specified register will be Read/Write. The details of the
Consecutive Adjacent Addressing is shown as below:
In MPI mode, when
CS
becomes low, IDT821068 treats the first byte
on CI pin as command, and the rest byte(s) as data. To write another
command, the
CS
must change from low to high to finish the previous
command and then change from high to low to indicate the start of the
next command. When a Read/Write operation is completed,
CS
must
be pulled to high in 8-bit time.
In MPI mode, the procedure of Consecutive Adjacent Addressing
can be stopped by
CS
signal at any time. When
CS
change from low
to high, the operation of the current Register and the next adjacent
registers will be aborted. But the results of previous operation are still
remained.
In GCI mode, the procedure of Consecutive Adjacent Addressing
can not be stopped once a command is initiated. For write command,
the number of bytes following the command must be the same as the
number of registers being written.
ADDRESSING GLOBAL REGISTER
The address of the 26 Global Registers is as the following:
00000 - 11000 (Global Register 1- 25)
11100 (Global Register 26)
It should be noted that the address of Global Register 26 is 11100
and not 11001, because the address space from 11001 to 11011 are
reserved.
For the adjacent 25 Global Registers, IDT821068 also provides a
Consecutive Adjacent Addressing for Read/Write operation, as it does
for Local Registers. In MPI mode, the procedure of Consecutive
Adjacent Addressing for Global Register also can be stopped by
CS
signal at any time as it does for Local Registers. But in GCI
mode, the procedure can not be stopped once a command is
initiated. For the 26th Global Register (address is 11100), once a
Read/Write procedure is completed,
CS
must be pulled high. It should
be noted that, in GCI mode, the Global Command for all 8 channels
can be transferred at any GCI time slot.
ADDRESSING COE-RAM
IDT821068 provides 40 words of Coe-RAM for per channel. They
are divided into 5 blocks, each block contains 8 words. The 5 blocks
are:
- IMF RAM (Word 0 - Word 7), for Impedance Matching Filter
coefficient;
- ECF RAM (Word 8 - Word 15), for Echo Cancellation Filter
coefficient;
- GIS RAM (Word 16 - Word 23), for Gain of Impedance Scaling;
- FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31), for
coefficient of Frequency Response Correction in Transmit Path and
Gain in Transmit Path;
- FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39), for
coefficient of Frequency Response Correction in Receive Path and
Gain in Receive Path.
Refer to APPENDIX I (Coe-RAM Address Mapping) for the Coe-
RAM address.
Each word in the Coe-RAM is 14-bit (b[13:0]) wide. To write a Coe-
RAM word, 16 bits (b[15:0]) (or, two 8-bit bytes) are needed to fulfill
with MSB first
,
but the lowest two bits (b[1:0]) will be ignored. When
being read, each Coe-RAM word will output 16 bits with MSB first, but
the last two bits (b[1:0]) are meaningless.
In MPI mode, when addressing Coe-RAM, Global Command 6
(Channel Enable) must be used first to specify the channel(s), then the
Address (b[4:0]) in the followed RAM Command indicates which block
of the Coe-RAM for the channel(s) will be addressed.
In GCI mode, both the location of time slot (determined by S1 and
S0 pin) and the b4 bit in Program Start Byte would indicate which
channel will be addressed.
The address in a Coe-RAM Command locates a block of Coe-
RAM. That is, when executing a Coe-RAM Command, then all 8
words in the block will be Read/Write automatically, with the highest
order word first.
In MPI mode, when read/write a Coe-RAM block, the procedure of
addressing words can be stopped by
CS
signal at any time. When
CS
change from low to high, the operation of the current word and the
next adjacent words will be aborted. But for previous operation, the
results are still remained.
ADDRESSING FSK-RAM
The FSK-RAM is consisted of 4 blocks, each block has eight 16-bit
words. The total 32 words of FSK-RAM are shared by the 8 channels,
only one channel can used it at one time.
To write a FSK-RAM word, 16 bits (or, two 8-bit bytes) are needed to
fulfill with MSB first
.
When being read, each FSK-RAM word in FSK-
RAM will output 16 bits with MSB first.
Table 4
Consecutive Adjacent Addressing
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