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參數(shù)資料
| 型號： | IDT72V3640L39268BBGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 1K X 36 OTHER FIFO, 5 ns, PBGA144 |
| 封裝： | 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144 |
| 文件頁數(shù)： | 39/46頁 |
| 文件大小： | 453K |
| 代理商： | IDT72V3640L39268BBGI |
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44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
NOVEMBER 2, 2005
Figure 33. TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
1
0
Select-
DR-Scan
Select-
IR-Scan
1
Capture-IR
0
Capture-DR
0
EXit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
0
1
4667 drw38
0
Shift-DR
0
Shift-IR
0
Pause-IR
0
1
Input = TMS
0
1
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
CAPTURE-DR
Data is loaded from the parallel input pins or core outputs into the Data
Register.
SHIFT-DR
Thepreviouslycaptureddataisshiftedinserially,LSBfirstattherisingedge
ofTCLKintheTDI/TDOpathandshiftedoutserially,LSBfirstatthefallingedge
of TCLK towards the output.
UPDATE-DR
The shifting process has been completed. The data is latched into their
parallel outputs in this state to be accessed through the internal bus.
EXIT1-DR / EXIT2-DR
Thisisatemporarycontrollerstate.IfTMSisheldhigh,arisingedgeapplied
toTCKwhileinthisstatecausesthecontrollertoentertheUpdate-DRstate.This
terminates the scanning process. All test data registers selected by the current
instruction retain their previous state unchanged.
PAUSE-DR
This controller state allows shifting of the test data register in the serial path
between TDI and TDO to be temporarily halted. All test data registers selected
by the current instruction retain their previous state unchanged.
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
similartoDataregisters.Theseinstructionsoperateontheinstructionregisters.
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by
TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
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| IDT72V3640L6PF | 功能描述:IC FIFO SS 1024X36 6NS 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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