參數(shù)資料
型號： IDT723626
廠商： Integrated Device Technology, Inc.
英文描述： Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
中文描述： 三重總線SyncFIFO的CMOS與巴士線匹配
文件頁數(shù)： 4/35頁
文件大?。?/td> 563K
代理商： IDT723626
4
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
AEA
Port A Data
Port A Almost-Empty
Flag
Port B Almost-Empty
Flag
Port A Almost-Full
Flag
Port C Almost-Full
Flag
Port B Data
Big-Endian/
First Word
Fall Through
Select
I/O 36-bit bidirectional data port for side A.
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
less than or equal to the value in the Almost-Empty A Offset register, X2.
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
less than or equal to the value in the Almost-Empty B Offset register, X1.
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
O
Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations in
FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.
O
18-bit output data port for side B.
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this
case, depending on the bus size, the
most
significant byte or word on Port A is read fromPort B first (A-to-B
data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select Little-Endian operation.
In this case, the
least
significant byte or word on Port A is read fromPort B first (A-to-B data flow) or is
written to Port C first (C-to-A data flow).
After Master Reset, this pin selects the timng mode. A HIGH on
FWFT
selects IDT Standard mode,a LOW
selects First Word Fall Through mode. Once the timng mode has been selected, the level on
FWFT
must
be static throughout device operation.
I
18-bit input data port for side C.
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincident to CLKB.
FFA
/IRA,
EFA
/ORA,
AFA
, and
AEA
are all synchronized to the LOW-to-HIGH
transition of CLKA.
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincident to CLKA.
EFB
/ORB and
AEB
are synchronized to the LOW-to-HIGH transition of CLKB.
I
CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous
or coincident to CLKA.
FFC
/IRC and
AFC
are synchronized to the LOW-to-HIGH transition of CLKC.
I
CSA
must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when
CSA
is HIGH.
I
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17
outputs are in the high-impedance state when
CSB
is HIGH.
O
This is a dual function pin. In the IDT Standard mode, the
EFA
function is selected.
EFA
indicates whether
or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the
presence of valid data on the A0-A35 outputs, available for reading.
EFA
/ORA is synchronized to the
LOW-to-HIGH transition of CLKA.
O
This is a dual function pin. In the IDT Standard mode, the
EFB
function is selected.
EFB
indicates whether
or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the
presence of valid data on the B0-B17 outputs, available for reading.
EFB
/ORB is synchronized to the
LOW-to-HIGH transition of CLKB.
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
O
This is a dual function pin. In the IDT Standard mode, the
FFA
function is selected.
FFA
indicates whether
or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory.
FFA
/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
O
This is a dual function pin. In the IDT Standard mode, the
FFC
function is selected.
FFC
indicates whether
or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC indicates whether or
not there is space available for writing to the FIFO2 memory.
FFC
/IRC is synchronized to the
LOW-to-HIGH transition of CLKC.
AEB
AFA
AFC
B0-B17
BE/
FWFT
C0-C17
CLKA
Port C Data
Port A Clock
CLKB
Port B Clock
CLKC
Port C Clock
CSA
Port A Chip Select
CSB
Port B Chip Select
EFA
/ORA
Port A Empty/
Output Ready Flag
EFB
/ORB
Port B Empty/
Output Ready Flag
ENA
FFA
/IRA
Port A Enable
Port A Full/
Input Ready Flag
FFC
/IRC
Port C Full/
Input Ready Flag
相關(guān)PDF資料
PDF描述
IDT723636L12PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723636L15PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646 CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L12PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L15PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723626L12PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L12PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L15PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L15PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723631L15PF 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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