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參數(shù)資料
| 型號： | IDT723626 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| 中文描述： | 三重總線SyncFIFO的CMOS與巴士線匹配 |
| 文件頁數(shù)： | 3/35頁 |
| 文件大小： | 563K |
| 代理商： | IDT723626 |
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3
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
bidirectional interface between mcroprocessors and/or buses with synchro-
nous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (
MBF1
and
MBF2
) to signal when
new mail has been stored.
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array and selects serial flag programmng, parallel flag program
mng, or one of three possible default flag offset settings, 8, 16 or 64. Each FIFO
has its own, independent Master Reset pin,
MRS1
and
MRS2
.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programmng method and partial flag default offsets) are retained. Partial Reset
is useful since it permts flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1
and
PRS2
.
These devices have two modes of operation: In the
IDT Standard
mode
, the first word written to an empty FIFO is deposited into the memory
array. A read operation is required to access that word (along with all other
words residing in memory). In the
First Word Fall Through mode
(FWFT),
the first word written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the BE/
FWFT
pin
during Master Reset determnes the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA
/ORA and
EFB
/ORB) and a combined Full/Input Ready Flag (
FFA
/IRA and
FFC
/IRC).
The
EF
and
FF
functions are selected in the IDT Standard mode.
EF
indicates
whether or not the FIFO memory is empty.
FF
shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA
and
AEB
) and
a programmable Almost-Full flag (
AFA
and
AFC
).
AEA
and
AEB
indicate when
a selected number of words remain in the FIFO memory.
AFA
and
AFC
indicate
when the FIFO contains more than a selected number of words.
FFA
/IRA,
FFC
/IRC,
AFA
and
AFC
are two-stage synchronized to the Port
Clock that writes data into its array.
EFA
/ORA,
EFB
/ORB,
AEA
, and
AEB
are
two-stage synchronized to the Port Clock that reads data fromits array.
Programmable offsets for
AEA
,
AEB
,
AFA
,
AFC
are loaded in parallel using Port
A or in serial via the SD input. The Serial Programmng Mode pin (
SPM
) makes
this selection. Three default offset settings are also provided. The
AEA
and
AEB
threshold can be set at 8, 16 or 64 locations fromthe empty boundary and the
AFA
and
AFC
threshold can be set at 8, 16 or 64 locations fromthe full boundary.
All these choices are made using the FS0 and FS1 inputs during Master Reset.
Two or more FIFOs may be used in parallel to create wider data paths.
Such a width expansion requires no additional, external components. Further-
more, two IDT723626/723636/723646 FIFOs can be combined with unidirec-
tional FIFOs capable of First Word Fall Through timng (i.e. the SuperSync FIFO
famly) to forma depth expansion.
If, at any time, the FIFO is not actively performng a function, the chip
will automatically power down. During the power down state, supply current
consumption (I
CC
) is at a mnimum Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT723626/723636/723646s are characterized for operation from
0
°
C to 70
°
C. Industrial temperature range (–40
°
C to +85
°
C) is available by
special order. They are fabricated using IDT’s high speed, submcron CMOS
technology.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT723636L12PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723636L15PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646 | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646L12PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646L15PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723626L12PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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