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參數(shù)資料
| 型號： | IDT723626 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| 中文描述： | 三重總線SyncFIFO的CMOS與巴士線匹配 |
| 文件頁數(shù)： | 11/35頁 |
| 文件大小： | 563K |
| 代理商： | IDT723626 |
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11
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SPM
FS1/
SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS
(1)
X2 AND Y2 REGlSTERS
(2)
H
H
H
↑
X
64
X
H
H
H
↑
↑
64
64
H
H
L
↑
X
16
X
H
H
L
↑
↑
16
16
H
L
H
↑
X
8
X
H
L
H
↑
↑
8
8
H
L
L
↑
↑
Parallel programmng via Port A
Parallel programmng via Port A
L
H
L
↑
↑
Serial programmng via SD
Serial programmng via SD
L
H
H
↑
↑
Reserved
Reserved
L
L
H
↑
↑
Reserved
Reserved
L
L
L
↑
↑
Reserved
Reserved
outputs, no read request necessary. Subsequent words must be accessed by
performng a formal read operation. Refer to Figure 4 (FIFO1 Master Reset)
and Figure 5 (FIFO2 Master Reset) for First Word Fall Through select timng
diagrams.
Following Master Reset, the level applied to the BE/
FWFT
input to choose
the desired timng mode must remain static throughout FIFO operation.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in these FIFOs are used to hold the offset values for the
Almost-Empty and Almost-Full flags. The Port B Almost-Empty flag (
AEB
) Offset
register is labeled X1 and the Port A Almost-Empty flag (
AEA
) Offset register is
labeled X2. The Port A Almost-Full flag (
AFA
) Offset register is labeled Y1 and
the Port C Almost-Full flag (
AFC
) Offset register is labeled Y2. The index of each
register name corresponds to its FIFO number. The Offset registers can be
loaded with preset values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial using the Serial
Data (SD) input (see Table 1).
SPM
, FS0/SD, and FS1/
SEN
function the same way in both IDT Standard
and FWFT modes.
PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, the Serial ProgramMode
(
SPM
) and at least one of the flag-select inputs must be HIGH during the LOW-
to-HIGH transition of its Master Reset (
MRS1
and
MRS2
) input. For example, to
load the preset value of 64 into X1 and Y1,
SPM
, FS0 and FS1 must be HIGH
when FlFO1 reset (
MRS1
) returns HIGH. Flag Offset registers associated with
FIFO2 are loaded with one of the preset values in the same way with FIFO2
Master Reset (
MRS2
) toggled simultaneously with FIFO1 Master Reset (
MRS1
).
For relevant Preset value loading timng diagrams, see Figure 4 and 5.
PARALLEL LOAD FROMPORT A
To programthe X1, X2, Y1, and Y2 registers fromPort A, performa Master
Reset on both FlFOs simultaneously with
SPM
HIGH and FS0 and FS1 LOW
during the LOW-to-HIGH transition of
MRS1
and
MRS2
. After this reset is
complete, the first four writes to FIFO1 do not store data in RAMbut load the Offset
registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the Offset
registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723626, IDT723636,
or IDT723646, respectively. The highest numbered input is used as the most
significant bit of the binary number in each case. Valid programmng values for
the registers range from1 to 252 for the IDT723626; 1 to 508 for the IDT723636;
and 1 to 1,020 for the IDT723646. After all the Offset registers are programmed
fromPort A, the Port C Full/Input Ready flag (
FFC
/IRC) is set HIGH, and both
FIFOs begin normal operation.
Refer to Figure 8 for a timng diagramillustration for parallel programmng
of the flag offset values.
SERIAL LOAD
To programthe X1, X2, Y1, and Y2 registers serially, initiate a Master
Reset with
SPM
LOW, FS0/SD LOW and FS1/
SEN
HIGH during the LOW-to-
HIGH transition of
MRS1
and
MRS2
. After this reset is complete, the X and Y
register values are loaded bit-wise through the FS0/SD input on each LOW-
to-HIGH transition of CLKA that the FS1/
SEN
input is LOW. There are 32-, 36-
, or 40-bit writes needed to complete the programmng for the IDT723626,
IDT723636, or IDT723646, respectively. The four registers are written in the
order Y1, X1, Y2 and finally, X2. The first-bit write stores the most significant bit
of the Y1 register and the last-bit write stores the least significant bit of the X2
register. Each register value can be programmed from1 to 252 (IDT723626),
1 to 508 (IDT723636), or 1 to 1,020 (IDT723646).
When the option to programthe Offset registers serially is chosen, the Port
A Full/Input Ready (
FFA
/IRA) flag remains LOW until all register bits are written.
FFA
/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (
FFC
/
IRC) flag also remains LOW throughout the serial programmng process, until
all register bits are written.
FFC
/IRC is set HIGH by the LOW-to-HIGH transition
of CLKC after the last bit is loaded to allow normal FIFO2 operation.
See Figure 9 timng diagram
Serial Programmng of the Almost-Full Flag
and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes)
.
NOTES:
1. X1 register holds the offset for
AEB
; Y1 register holds the offset for
AFA
.
2. X2 register holds the offset for
AEA
; Y2 register holds the offset for
AFC
.
TABLE 1 FLAG PROGRAMMING
相關(guān)PDF資料 |
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|---|---|
| IDT723636L12PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723636L15PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646 | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646L12PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646L15PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723626L12PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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