參數(shù)資料
型號(hào)： IDT723626
廠商： Integrated Device Technology, Inc.
英文描述： Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
中文描述： 三重總線SyncFIFO的CMOS與巴士線匹配
文件頁(yè)數(shù)： 12/35頁(yè)
文件大?。?/td> 563K
代理商： IDT723626
12
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
CSA
W/
R
A
ENA
MBA
CLKA
DATA A (A0-A35) I/O
PORT FUNCTION
H
X
X
X
X
High-Impedance
None
L
H
L
X
X
Input
None
L
H
H
L
↑
Input
FIFO1 write
L
H
H
H
↑
Input
Mail1 write
L
L
L
L
X
Output
None
L
L
H
L
↑
Output
FIFO2 read
L
L
L
H
X
Output
None
L
L
H
H
↑
Output
Mail2 read (set
MBF2
HIGH)
CSB
RENB
MBB
CLKB
DATA B (B0-B17) OUTPUTS
PORT FUNCTION
H
X
X
X
High-Impedance
None
L
L
L
X
Output
None
L
H
L
↑
Output
FIFO1 read
L
L
H
X
Output
None
L
H
H
↑
Output
Mail1 read (set
MBF1
HIGH)
TABLE 4 PORT C ENABLE FUNCTION TABLE
WENC
MBC
CLKC
TABLE 3 PORT B ENABLE FUNCTION TABLE
DATA C (C0-C17) INPUTS
PORT FUNCTION
H
L
↑
Input
FIFO2 write
H
H
↑
Input
Mail2 write
L
L
X
Input
None
L
H
X
Input
None
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) outputs is controlled by Port A Chip
Select (
CSA
) and Port A Write/Read Select (W/
R
A). The A0-A35 outputs are
in the High-impedance state when either
CSA
or W/
R
A is HIGH. The A0-A35
outputs are active when both
CSA
and W/
R
A are LOW.
Data is loaded into FIFO1 fromthe A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA
is LOW, W/
R
A is HIGH, ENA is HIGH, MBA is
LOW, and
FFA
/IRA is HIGH. Data is read fromFIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSA
is LOW, W/
R
A is LOW, ENA
is HIGH, MBA is LOW, and
EFA
/ORA is HIGH (see Table 2). FIFO reads and
writes on Port A are independent of any concurrent Port B and Port C operation.
The state of the Port B data (B0-B17) outputs is controlled by the Port B Chip
Select (
CSB
). The B0-B17 outputs are in the high-impedance state when
CSB
is HIGH. The B0-B17 outputs are active when
CSB
is LOW.
Data is read fromFIFO1 to the B0-B17 outputs by a LOW-to-HIGH transition
of CLKB when
CSB
is LOW, RENB is HIGH, MBB is LOW and
EFB
/ORB is
HIGH (see Table 3). FIFO reads on Port B are independent of any concurrent
Port A and Port C operations.
Data is loaded into FIFO2 fromthe C0-C17 inputs on a LOW-to-HIGH
transition of CLKC when WENB is HIGH, MBC is LOW, and
FFC
/IRC is HIGH
(see Table 4). FIFO writes on Port C are independent of any concurrent Port A
and Port B operation.
The setup and hold time constraints for
CSA
and W/
R
A with regard to CLKA
as well as
CSB
with regard to CLKB are only for enabling write and read
operations and are not related to high-impedance control of the data outputs.
If ENA is LOW during a clock cycle, either
CSA
or W/
R
A may change states
during the setup and hold time window of the cycle. This is also true for
CSB
when RENB is LOW.
When operating the FIFO in FWFT mode and the Output R
eady flag is
LOW, the next word written is automatically sent to the FIFO’s output register
by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag
HIGH. When the Output Ready flag is HIGH, subsequent data is clocked to the
output registers only when a read is selected using
CSA,
W/
R
A
,
ENA and MBA
at Port A or using
CSB
, RENB and MBB at Port B.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of
the read clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using
CSA
W/
R
A ENA and MBA at Port
A or using
CSB
, RENB and MBB at Port B. Relevant write and read timng
diagrams for Port A can be found in Figure 10 and 15. Relevant read and write
timng diagrams for Port B and Port C, together with Bus-Matching and Endian
Select operations can be found in Figures 11 to 14.
TABLE 2 PORT A ENABLE FUNCTION TABLE
相關(guān)PDF資料
PDF描述
IDT723636L12PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723636L15PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646 CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L12PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L15PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723626L12PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L12PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L15PF 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723626L15PF8 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723631L15PF 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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