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參數(shù)資料
| 型號： | IDT723626 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| 中文描述： | 三重總線SyncFIFO的CMOS與巴士線匹配 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 563K |
| 代理商： | IDT723626 |
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10
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
SIGNAL DESCRIPTION
MASTER RESET (
MRS1
,
MRS2
)
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
MRS1
and
MRS2
simultaneously. Afterwards, the FIFO1
memory of the IDT723626/723636/723646 undergoes a complete reset by
taking its associated Master Reset (
MRS1
) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(
MRS2
) input LOW for at least four Port A Clock (CLKA) and four Port C Clock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch asyn-
chronously to the clocks. A Master Reset initializes the associated read and write
pointers to the first location of the memory and forces the Full/Input Ready flag
(
FFA
/IRA,
FFC
/IRC) LOW, the Empty/Output Ready flag (
EFA
/ORA,
EFB
/
ORB) LOW, the Almost-Empty flag (
AEA
,
AEB
) LOW, and the Almost-Full flag
(
AFA
,
AFC
) HIGH. A Master Reset also forces the associated Mailbox Flag
(
MBF1
,
MBF2
) of the parallel mailbox register HIGH. After a Master Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two Write clock cycles. Then the
FIFO is ready to be written to.
A LOW-to-HIGH transition on a FlFO1 Master Reset (
MRS1
,
MRS2
) input
latches the value of the Big-Endian (BE) input for determning the order by which
bytes are transferred through ports B and C. It also latches the values of the Flag
Select (FS0, FS1) and Serial Programmng Mode (
SPM
) inputs for choosing
the Almost-Full and Almost-Empty offset programmng mode.
A LOW-to-HIGH transition on the FIFO2 Master Reset (
MRS2
) clears the flag
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2 Master
Reset input (
MRS2
) latches the value of the Big-Endian (BE) input for Ports B and
C and also latches the values of the Flag Select (FS0, FS1) and Serial Programmng
Mode (
SPM
) inputs for choosing the Almost-Full and Almost-Empty offset program
mng method (for details see Table 1,
Flag Programmng
, and
Almost-Empty and
Almost-Full Flag Offset Programmng
section). The relevant Master Reset timng
diagrams can be found in Figure 4 and 5.
Note that MBC must be HIGH during Master Reset (until
FFA
/IRA and
FFC
/
IRC go HIGH). MBA and MBB are "don't care" inputs
1
during Master Reset.
PARTIAL RESET (
PRS1
,
PRS2
)
The FIFO1 memory of these devices undergoes a limted reset by taking
its associated Partial Reset (
PRS1
) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a limted reset by taking its associated Partial Reset (
PRS2
)
input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC)
LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously
to the clocks. A Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (
FFA
/IRA,
FFC
/IRC) LOW, the Empty/Output
Ready flag (
EFA
/ORA,
EFB
/ORB) LOW, the Almost-Empty flag (
AEA
,
AEB
)
LOW, and the Almost-Full flag (
AFA
,
AFC
) HIGH. A Partial Reset also forces
the Mailbox Flag (
MBF1
,
MBF2
) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two Write clock
cycles.
Whatever flag offsets, programmng method (parallel or serial), and timng
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will remain unchanged upon completion of the
reset operation. A Partial Reset may be useful in the case where reprogrammng
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timng diagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT
)
ENDIAN SELECTION
This is a dual purpose pin. At the time of Master Reset, the BE select
function is active, permtting a choice of Big- or Little-Endian byte arrange-
ment for data written to Port C or read fromPort B. This selection determnes
the order by which bytes (or words) of data are transferred through those
ports. For the following illustrations, note that both ports B and C are configured
to have a byte (or a word) bus size.
A HIGH on the BE/
FWFT
input when the Master Reset (
MRS1
,
MRS2
) inputs
go fromLOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction fromPort A to Port B, the most significant byte (word) of
the long word written to Port A will be read fromPort B first; the least significant
byte (word) of the long word written to Port A will be read fromPort B last. When
data is moving in the direction fromPort C to Port A, the byte (word) written to
Port C first will be read fromPort A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read fromPort A as the least
significant byte (word) of the long word.
A LOW on the BE/
FWFT
input when the Master Reset (
MRS1
,
MRS2
) inputs
go fromLOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction fromPort A to Port B, the least significant byte (word) of
the long word written to Port A will be read fromPort B first; the most significant
byte (word) of the long word written to Port A will be read fromPort B last. When
data is moving in the direction fromPort C to Port A, the byte (word) written to
Port C first will be read fromPort A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read fromPort A as the most
significant byte (word) of the long word. Refer to Figures 2 and 3 for illustrations
of the BE
function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timng diagrams.
TIMING MODE SELECTION
After Master Reset, the FWFT select function is available, permtting a
choice between two possible timng modes: IDT Standard mode or First
Word Fall Through (FWFT) mode. Once the Master Reset (
MRS1
,
MRS2
)
input is HIGH, a HIGH on the BE/
FWFT
input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKC (for FIFO2) will select IDT Standard
mode. This mode uses the Empty Flag function (
EFA
,
EFB
) to indicate whether
or not there are any words present in the FIFO memory. It uses the Full Flag
function (
FFA
,
FFC
) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read fromthe FIFO,
including the first, must be requested using a formal read operation.
Once the Master Reset (
MRS1
,
MRS2
) input is HIGH, a LOW on the BE/
FWFT
input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to the data
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
unused inputs) must not be left open, rather they must be either HIGH or LOW.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723626L12PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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