參數(shù)資料
型號(hào)： IDT723613L20PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
中文描述： 64 X 36 OTHER FIFO, 12 ns, PQFP120
封裝： TQFP-120
文件頁數(shù)： 4/26頁
文件大小： 193K
代理商： IDT723613L20PF
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Symbol
A
0
-A
35
AE
Name
I/O
I/O
O
Port B
O
Port A
I/O
I
Description
Port A Data
Almost-Empty Flag
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit
words in the FIFO is less than or equal to the value in the offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty location
in the FIFO is less than or equal to the value in the offset register, X.
36-bit bidirectional data port for side B
Selects the bytes on port B used during byte or word FIFO reads. A LOW on
BE
selects the most significant
bytes on B
0
-B
35
for use, and a HIGH selects the least significant bytes.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB.
FF
and
AF
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or
coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the
LOW-to-HIGH transition of CLKB.
EF
and
AE
are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The
A
0
-A
35
outputs are in the high-impedance state when
CS
A is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B
0
-B
35
outputs are in the high-impedance state when
CSB
is HIGH.
EF
is synchronized to the LOW-to-HIGH transition of CLKB. When
EF
is LOW, the FIFO is empty, and
reads fromits memory are disabled. Data can be read fromthe FIFO to its output register when
EF
is
HIGH.
EF
is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition
of CLKB after data is loaded into empty FIFO memory.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FF
is synchronized to the LOW-to-HIGH transition of CLKA. When
FF
is LOW, the FIFO is full, and writes
to its memory are disabled.
FF
is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after reset.
The LOW-to-HIGH transition of
RST
latches the values of FS
0
and FS
1
, which loads one of four preset
values into the Almost-Full flag and Almost-Empty flag offsets.
A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35
outputs are active, mail2 register data is output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the
mail1 register are inhibited while
MBF1
is set LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of
CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH.
MBF1
is set HIGH when the
device is reset.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to
the mail2 register are inhibited while
MBF2
is set LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition
of CLKA when a port A read is selected and MBA is HIGH.
MBF2
is set HIGH when the device is reset.
Odd parity is checked on each port when ODD/
EVEN
is HIGH, and even parity is checked when ODD
EVEN
is LOW. ODD/
EVEN
also selects the type of parity generated for each port if parity generation is
enabled for a read operation.
When any byte applied to termnals A
0
-A
35
fails parity,
PEFA
is LOW. Bytes are organized as A
0
-A
8
, A
9
-A
17
,
A
18
-A
26
, and A
27
-A
35
, with the most significant bit of each byte serving as the parity bit. The type of parity
checked is determned by the state of the ODD/
EVEN
input. The parity trees used to check the A
0
-A
35
inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore,
if a mail2 read with parity generation is set up by having
CSA
LOW, ENA HIGH, W/
R
A LOW, MBA HIGH
and PGA HIGH, the
PEFA
flag is forced HIGH regardless of the state of the A
0
-A
35
inputs.
When any valid byte applied to termnals B
0
-B
35
fails parity,
PEFB
is LOW. Bytes are organized as B
0
-B
8
,
B
9
-B
17
, B18-B26, and B
27
-B
35
, with the most significant bit of each byte serving as the parity bit. A byte is
valid when it is used by the bus size selected for port B. The type of parity checked is determned by the
state of the ODD/
EVEN
input. The parity trees used to check the B
0
-B
35
inputs are shared by the mail1
register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity
generation is set up by having
CSB
LOW, ENB HIGH, W/
R
B LOW, SIZ1 and SIZ0 HIGH and PGB
HIGH, the
PEFB
flag is forced HIGH regardless of the state of the B
0
-B
35
inputs.
AF
Almost-Full Flag
B
0
-B
35
B E
Port B Data
Big-Endian Select
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
Port A Chip Select
I
CSB
Port B Chip Select
I
EF
Empty Flag
O
Port B
ENA
ENB
FF
Port A Enable
Port B Enable
Full Flag
I
I
O
Port A
FS
1
, FS
0
Flag Offset Selects
I
MBA
Port A Mailbox Select
I
MBF1
Mail1 Register Flag
O
MBF2
Mail2 Register Flag
O
ODD/
EVEN
Odd/Even Parity Select
I
PEFA
Port A Parity Error Flag
O
(Port A)
PEFB
Port B Parity Error Flag
O
(PortB)
PIN DESCRIPTION
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參數(shù)描述
IDT723613L20PF8 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723613L20PFI 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723613L20PFI8 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723613L20PQF 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723613L20PQFI 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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