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參數(shù)資料
| 型號(hào)： | IDT723613L20PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 |
| 中文描述： | 64 X 36 OTHER FIFO, 12 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 11/26頁 |
| 文件大?。?/td> | 193K |
| 代理商： | IDT723613L20PF |
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11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
Number of 36-Bit
Words in the FIFO
(1)
Synchronized
to CLKB
Synchronized
to CLKA
EF
AE
AF
FF
0
L
L
H
H
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
H
H
H
H
(64 – X) to 63
H
H
L
H
64
H
H
L
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
TABLE 3 PORT B ENABLE FUNCTION TABLE
CSB
W/
R
B
ENB
SIZ1, SIZ0
H
X
X
X
L
H
L
X
L
H
H
One, both LOW
L
H
H
Both HIGH
L
L
L
One, both LOW
L
L
H
One, both LOW
L
L
L
Both HIGH
L
L
H
Both HIGH
CLKB
X
X
↑
↑
X
↑
X
↑
B
0
-B
35
Outputs
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output register
Active, FIFO output register
Active, mail1 register
Active mail1 register
Port Function
None
None
None
Mail2 write
None
FIFO read
None
Mail1 read (set
MBF1
HIGH)
TABLE 4 FIFO FLAG OPERATION
FULL FLAG (
FF
)
The FIFO Full Flag is synchronized to the port clock that writes data to its array
(CLKA). When the
FF
is HIGH, a SRAMlocation is free to receive new data.
No memory locations are free when the
FF
is LOW and attempted writes to the
FIFO are ignored.
Each time a word is written to the FIFO, its write-pointer is incremented.
The state machine that controls the
FF
monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAMstatus is full, full-1,
or full-2. Fromthe time a word is read fromthe FIFO, its previous memory
location is ready to be written in a mnimumof three CLKA cycles. Therefore,
a
FF
is LOW if less than two CLKA cycles have elapsed since the next
memory write location has been read. The second LOW-to-HIGH transition
on the
FF
synchronizing clock after the read sets the
FF
HIGH and data can
be written in the following clock cycle.
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle
of a read if the clock transition occurs at time t
SKEW1
or greater after the read.
Otherwise, the subsequent clock cycle can be the first synchronization cycle
(see Figure 11).
ALMOST-EMPTY FLAG (
AE
)
The FIFO Almost-Empty flag is synchronized to the port clock that reads
data fromits array (CLKB). The state machine that controls the
AE
flag
monitors a write-pointer and read-pointer comparator that indicates when
the FIFO SRAMstatus is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the value of the Almost-Full and
Almost-Empty Offset register (X). This register is loaded with one of four
preset values during a device reset (see reset above). The
AE
flag is LOW
when the FIFO contains X or less long words in memory and is HIGH when
the FIFO contains (X+1) or more long words.
Two LOW-to-HIGH transitions on the port B Clock (CLKB) are required after
a FIFO write for the
AE
flag to reflect the new level of fill. Therefore, the
AE
flag
of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles
have not elapsed since the write that filled the memory to the (X+1) level. The
AE
flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB
begins the first synchronization cycle if it occurs at time t
SKEW2
or greater after
the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB
cycle can be the first synchronization cycle (see Figure 12).
ALMOST FULL FLAG (
AF
)
The FIFO Almost-Full flag is synchronized to the port clock that writes data
to its array (CLKA). The state machine that controls an
AF
flag monitors a
write-pointer and read-pointer comparator that indicates when the FIFO
SRAMstatus is almost -full, almost- full-1, or almost-full-2. The almost-full
state is defined by the value of the Almost-Full and Almost-Empty Offset
register (X). This register is loaded with one of four preset values during a
device reset (see reset above). The
AF
flag is LOW when the FIFO contains
(64-X) or more long words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less long words.
Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required
after a FIFO read for the
AF
flag to reflect the new level of fill. Therefore, the
AF
flag of a FIFO containing [64-(X+1)] or less words remains LOW if two
CLKA cycles have not elapsed since the read that reduced the number of
long words in memory to [64-(X+1)]. The
AF
flag is set HIGH by the second
CLKA LOW-to-HIGH transition after the FIFO read that reduces the number
of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA
begins the first synchronization cycle if it occurs at time t
SKEW2
or greater after
the read that reduces the number of long words in memory to [64-(X+1)].
Otherwise, the subsequent CLKA cycle can be the first synchronization
cycle (see Figure 13).
MAILBOX REGISTERS
Two 36-bit bypass registers (mail1, mail2) are on the IDT723613 to pass
command and control information between port A and port B without putting
it in queue. A LOW-to-HIGH transition on CLKA writes A
0
-A
35
data to the
mail1 register when a port A write is selected by
CSA
, W/
R
A, and ENA (with
MBA HIGH). A LOW-to-HIGH transition on CLKB writes B
0
-B
35
data to the
mail2 register when a port B write is selected by
CSB
, W/
R
B, and ENB (and
both SIZ0 and SIZ1 are HIGH). Writing data to a mail register sets its
corresponding flag (
MBF1
or
MBF2
) LOW. Attempted writes to a mail
register are ignored while its mail flag is LOW.
When the port B data (B
0
-B
35
) outputs are active, the data on the bus comes
fromthe FIFO output register when either one or both SIZ1 and SIZ0 are LOW
and fromthe mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1
Register Flag (
MBF1
) is set HIGH by a rising CLKB edge when a port B read
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| IDT723613L20PF8 | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PFI | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PFI8 | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PQF | 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PQFI | 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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