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參數(shù)資料
| 型號： | IDT723613L20PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 |
| 中文描述： | 64 X 36 OTHER FIFO, 12 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大?。?/td> | 193K |
| 代理商： | IDT723613L20PF |
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12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT723613 CMOS CLOCKED FIFO WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36
is selected by
CSB
, W/
R
B, and ENB, (and both SIZ1 and SIZ0 HIGH). The
Mail2 Register Flag (
MBF2
) is set HIGH by a rising CLKA edge when a port
A read is selected by
CSA
, W/
R
A, and ENA (with MBA HIGH). The data in a
mail register remains intact after it is read and changes only when new data is
written to the register.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
bit byte format for data read fromthe FIFO. Word- and byte-size bus
selections can utilize the most significant bytes of the bus (Big-Endian) or
least significant bytes of the bus (Little-Endian). Port B bus-size can be
changed dynamcally and synchronous to CLKB to communicate with
peripherals of various bus widths.
The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the
Big-Endian select (
BE
) input are stored on each CLKB LOW-to-HIGH
transition. The stored port B bus-size selection is implemented by the next
rising edge on CLKB according to Figure 2.
Only 36-bit long-word data is written to or read fromthe FIFO memory on
the IDT723613. Bus-matching operations are done after data is read from
the FIFO RAM. Port B bus sizing does not apply to mail register operations.
BUS-MATCHING FIFO READS
Data is read fromthe FIFO RAMin 36-bit long-word increments. If a long-
word bus-size is implemented, the entire long word immediately shifts to the
FIFO output register upon a read. If byte or word size is implemented on port
B, only the first one or two bytes appear on the selected portion of the FIFO
output register, with the rest of the long word stored in auxiliary registers. In
this case, subsequent FIFO reads with the same bus-size implementation
output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
Each FIFO read with a new bus-size implementation automatically un-
loads data fromthe FIFO RAMto its output register and auxiliary registers.
Therefore, implementing a new port B bus-size and performng a FIFO read
before all bytes or words stored in the auxiliary registers have been read
results in a loss of the unread data in these registers.
When reading data fromFIFO in byte or word format, the unused B
0
-B
35
outputs remain inactive but static, with the unused FIFO output register bits
holding the last data value to decrease power consumption.
BYTE SWAPPING
The byte-order arrangement of data read fromthe FIFO can be changed
synchronous to the rising edge of CLKB. Byte-order swapping is not
available for mail register data. Four modes of byte-order swapping (includ-
ing no swap) can be done with any data port size selection. The order of the
bytes are rearranged within the long word, but the bit order within the bytes
remains constant.
Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs
on a CLKB rising edge that reads a new long word fromthe FIFO. The byte
order chosen on the first byte or first word of a new long word read fromthe
FIFO is maintained until the entire long word is transferred, regardless of the
SW0 and SW1 states during subsequent reads. Figure 4 is an example of
the byte-order swapping available for long word reads. Performng a byte
swap and bus-size simultaneously for a FIFO read first rearranges the bytes
as shown in Figure 4, then outputs the bytes as shown in Figure 2.
PORT-B MAIL REGISTER ACCESS
In addition to selecting port B bus sizes for FIFO reads, the port B bus Size
select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and
SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and
the mail2 register is accessed for a port B long-word write. The mail register is
accessed immediately and any bus-sizing operation that can be underway is
unaffected by the mail register access. After the mail register access is complete,
the previous FIFO access can resume in the next CLKB cycle. The logic diagram
in Figure 3 shows the previous bus-size selection is preserved when the mail
registers are accessed fromport B. A port B bus-size is implemented on each
rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and
BE
_Q.
PARITY CHECKING
The port A data inputs (A
0
-A
35
) and port B data inputs (B
0
-B
35
) each have
four parity trees to check the parity of incomng (or outgoing) data. A parity
failure on one or more bytes of the port A data bus is reported by a low level
on the port A Parity Error Flag (
PEFA
). A parity failure on one or more bytes
of the port B data inputs that are valid for the bus-size implementation is
reported by a low level on the port B Parity Error Flag (
PEFB
). Odd or Even
parity checking can be selected, and the Parity Error Flags can be ignored
if this feature is not desired.
Parity status is checked on each input bus according to the level of the
Odd/Even parity (ODD/
EVEN
) select input. A parity error on one or more
valid bytes of a port is reported by a LOW level on the corresponding port
Parity Error Flag (
PEFA
,
PEFB
) output. Port A bytes are arranged as A
0
-A
8
,
A
9
-A
17
, A
18
-A
26
, and A
27
-A
35
, and port B bytes are arranged as B
0
-B
8
, B
9
-
B
17
, B
18
-B
26
, and B
27
-B
35
, and its valid bytes are those used in a port B bus
size implementation. When Odd/Even parity is selected, a port Parity Error
Flag (
PEFA
,
PEFB
) is LOW if any byte on the port has an odd/even number
of LOW levels applied to its bits.
The four parity trees used to check the A
0
-A
35
inputs are shared by the
mail2 register when parity generation is selected for port-A reads (PGA = HIGH).
When a port A read fromthe mail2 register with parity generation is selected with
CSA
LOW, ENA HIGH, W/
R
A LOW, MBA HIGH, and PGA HIGH, the port A
Parity Error Flag (
PEFA
) is held HIGH regardless of the levels applied to the
A
0
-A
35
inputs. Likewise, the parity trees used to check the B
0
-B
35
inputs are
shared by the mail1 register when parity generation is selected for port B reads
(PGB = HIGH). When a port B read fromthe mail1 register with parity generation
is selected with
CSB
LOW, ENB HIGH, W/
R
B LOW, both SIZ0 and SIZ1 HIGH,
and PGB HIGH, the port B Parity Error Flag (
PEFB
) is held HIGH regardless
of the levels applied to the B
0
-B
35
inputs.
PARITY GENERATION
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generate select (PGB) enables the IDT723613 to generate parity bits for
port reads froma FIFO or mailbox register. Port A bytes are arranged as A
0
-
A
8
, A
9
-A
17
, A
18
-A
26
, and A
27
-A
35
, with the most significant bit of each byte
used as the parity bit. Port B bytes are arranged as B
0
-B
8
, B
9
-B
17
, B
18
-B
26
,
and B
27
-B
35
, with the most significant bit of each byte used as the parity bit.
A write to a FIFO or mail register stores the levels applied to all nine inputs
of a byte regardless of the state of the Parity Generate select (PGA, PGB)
inputs. When data is read froma port with parity generation selected, the
lower eight bits of each byte are used to generate a parity bit according to the
level on the ODD/
EVEN
select. The generated parity bits are substituted for
the levels originally written to the most significant bits of each byte as the word
is read to the data outputs.
Parity bits for FIFO data are generated after the data is read fromSRAM
and before the data is written to the output register. Therefore, the port A Parity
Generate select (PGA) and Odd/Even parity select (ODD/
EVEN
) have setup
and hold time constraints to the port A Clock (CLKA) and the port B Parity
Generate select (PGB) and ODD/
EVEN
select have setup and hold time
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| IDT723613L20PF8 | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PFI | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PFI8 | 功能描述:IC CLOCKED FIFO 64X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PQF | 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723613L20PQFI | 功能描述:IC CLOCKED FIFO 64X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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