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參數(shù)資料
| 型號(hào)： | IDT72131L35P |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 35 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 7/13頁(yè) |
| 文件大?。?/td> | 126K |
| 代理商： | IDT72131L35P |
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7
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
NOTE:
1. Once
EF
has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until
EF
goes HIGH.
NOTE:
1. SOCP should not be clocked until
EF
goes HIGH.
Figure 6. Empty Boundary Condition Timing
2751 drw 09
SOCP
t
WEF
0
1
n – 1
W
EF
SO
t
SOCEF
t
REFSO
DATA
IN
(1)
t
SOLZ
t
SOPD
Figure 5. Empty Flag from Last Read to First Write
2751 drw 08
SOCP
t
WEF
LAST READ
NO READ
FIRST WRITE
ADDITIONAL
WRITES
FIRST READ
0
1
n – 1
0
1
n – 1
W
EF
t
SOPD
SO
VALID
VALID
(1)
t
SOCEF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72131L50P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141 | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141L35P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141L50P | 3/8 Pin 100mA Adjustable Positive Voltage Regulator 8-SOIC 0 to 125 |
| IDT72132 | CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72131L50CB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72131L50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72156 | 制造商:IDT 功能描述:72156 |
| IDT7216L25FB | 制造商:Integrated Device Technology Inc 功能描述:MULTIPLIER, 64 Pin, Ceramic, Quad CERPAK |
| IDT7216L55GB | 制造商:Integrated Device Technology Inc 功能描述: |
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