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參數(shù)資料
| 型號： | IDT72131L35P |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 35 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 126K |
| 代理商： | IDT72131L35P |
5.34
2
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Retransmit
Clock
Next Read
Expansion
STATUS FLAGS
Number of Words in FIFO
IDT72131
0
1-255
256-1024
1025-1792
1793-2047
2048
IDT72141
0
1-511
512-2048
2049-3584
3585-4095
4096
FF
AEF
HF
EF
H
H
H
H
H
L
L
L
H
H
L
L
H
H
H
L
L
L
L
H
H
H
H
H
2751 tbl 02
Almost-Full Flag
Expansion Out/
Half-Full Flag
Q
7
and
Q
8
V
CC
GND
PIN DESCRIPTIONS
Symbol
D
0
–D
8
Inputs
RS
Reset
Name
I/O
I
I
Description
Data inputs for 9-bit wide data.
When
RS
is set LOW, internal READ and WRITE pointers are set to the first location of the RAM
array.
HF
and
FF
go HIGH, and
AEF
and
EF
go LOW. A reset is required before an initial WRITE
after power-up.
W
must be HIGH and SOCP must be LOW during
RS
cycle.
A write cycle is initiated on the falling edge of WRITE if the Full Flag (
FF
) is not set. Data set-
up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored
in the RAM array sequentially and independently of any ongoing read operation.
A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (
EF
) is not set. In
both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together.
To program the Serial Out data word width , connect
NR
with one of the Data Set pins (Q
4
, Q
6
,
Q
7
and Q
8
). For example,
NR
- Q
7
programs for a 8-bit Serial Out word width.
This is a dual purpose input. In the single device configuration (
XI
grounded), activating retransmit
(
FL
/
RT
-LOW) will set the internal READ pointer to the first location. There is no effect on the
WRITE pointer.
W
must be high and SOCP must be low before setting
FL
/
RT
LOW. Retransmit
is not compatible with depth expansion. In the depth expansion configuration,
FL
/
RT
grounded
indicates the first activated device.
In the single device configuration,
XI
is grounded. In depth expansion or daisy chain expansion,
XI
is connected to
XO
(expansion out) of the previous device.
In the Serial Output Expansion mode, the SOX pin of the least significant device is tied HIGH.
The SOX pin of all other devices is connected to the Q
8
pin of the previous device. Data is then
clocked out least significant bit first. For single device operation, SOX is tied HIGH.
Serial data is output on the Serial Output (SO) pin. Data is clocked out Least Significant Bit first.
In the Serial Width Expansion mode the SO pins are tied together and each SO pin is tristated
at the end of the byte.
When
FF
goes LOW, the device is full and further WRITE operations are inhibited. When
FF
is
HIGH, the device is not full.
When
EF
goes LOW, the device is empty and further READ operations are inhibited. When
EF
is HIGH, the device is not empty. See the description on page 6 for more details.
When
AEF
is LOW, the device is empty to 1/8 full or 7/8 to completely full. When
AEF
is HIGH,
the device is greater than 1/8 full, but less than 7/8 full.
This is a dual-purpose output. In the single device configuration (
XI
grounded), the device is more
than half full when HF is LOW. In the depth expansion configuration (
XO
connected to
XI
of the
next device), a pulse is sent from
XO
to
XI
when the last location in the RAM array is filled.
The appropriate Data Set pin (Q
4
, Q
6
, Q
7
and Q
8
) is connected to
NR
to program the Serial Out
data word width. For example: Q
6
-
NR
programs a 7-bit word width, Q
8
-
NR
programs a 9-bit
word width, etc.
Single Power Supply of 5V.
Single ground at 0V.
W
Write
I
SOCP
Serial Output
I
NR
I
FL
/
RT
First Load/
I
XI
Expansion In
I
SOX
Serial Output
I
SO
Serial Output
O
FF
Full Flag
O
EF
Empty Flag
O
AEF
Almost-Empty/
O
XO/HF
O
Q
4
, Q
6
,
Data Set
O
Power Supply
Ground
2751 tbl 01
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|---|---|
| IDT72131L50P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141 | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
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