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參數(shù)資料
| 型號(hào)： | IDT72131L35P |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| 中文描述： | 2K X 9 OTHER FIFO, 35 ns, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大小： | 126K |
| 代理商： | IDT72131L35P |
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5.34
6
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Figure 2. Write Operation
Figure 3. Read Operation
Figure 4. Full Flag from Last Write to First Read
2751 drw 05
W
t
WC
D
0–8
t
WPW
t
WR
t
DS
t
DH
2751 drw 06
SOCP
t
SOCW
SOX
SO
SO
(1)
(2)
1/f
SOCP
t
SOCW
0
1
n – 1
t
SOX
t
SOHZ
t
SOLZ
t
SOPD
2751 drw 07
SOCP
t
SOCFF
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST WRITE
0
1
n – 1
0
1
n – 1
t
WFF
W
FF
NOTES:
1. This timing applies to the Active Device in Width Expansion Mode.
2. This timing applies to Single Device Mode at Empty Boundary (
EF
= LOW) and the Next Active Device in Width Expansion Mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72131L50P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141 | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141L35P | CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9 |
| IDT72141L50P | 3/8 Pin 100mA Adjustable Positive Voltage Regulator 8-SOIC 0 to 125 |
| IDT72132 | CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72131L50CB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72131L50P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT72156 | 制造商:IDT 功能描述:72156 |
| IDT7216L25FB | 制造商:Integrated Device Technology Inc 功能描述:MULTIPLIER, 64 Pin, Ceramic, Quad CERPAK |
| IDT7216L55GB | 制造商:Integrated Device Technology Inc 功能描述: |
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