參數(shù)資料
型號: IDT70V7519S166BF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述: 256K X 36 DUAL-PORT SRAM, 12 ns, PBGA208
封裝: FBGA-208
文件頁數(shù): 10/22頁
文件大?。?/td> 490K
代理商: IDT70V7519S166BF
6.42
18
IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1,6)
NOTES:
1.
CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when
ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during
REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5.
CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.
7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
ADDRESS
An
CLK
DATAIN
Dn
Dn + 1
Dn + 2
ADS
CNTEN
tCH2
tCL2
tCYC2
5618 drw 18
INTERNAL
(3)
ADDRESS
An
(5)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
tSA
tHA
tSAD tHAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
tSD tHD
tSCN tHCN
Timing Waveform of Counter Repeat for Flow Through Mode(2,6,7)
ADDRESS
An
tCYC2
CLK
DATAIN
R/W
REPEAT
5618 drw 19
INTERNAL
(3)
ADDRESS
ADS
CNTEN
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
DATAOUT
tSA tHA
,
An
tSAD tHAD
tSW tHW
tSCN tHCN
tSRPT tHRPT
tSD tHD
tCD1
An+1
An+2
An
An+1
An+2
D0
D1
D2
D3
An
An+1
An+2
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
(4)
相關(guān)PDF資料
PDF描述
IDT70V7519S166BFI HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S166DR HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S166DRI HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S200DR HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S200DRI HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
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