參數(shù)資料
型號： IDT70V7519S166DRI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述： 256K X 36 DUAL-PORT SRAM, 12 ns, PQFP208
封裝： PLASTIC, QFP-208
文件頁數(shù)： 1/22頁
文件大?。?/td> 490K
代理商： IDT70V7519S166DRI
2002 Integrated Device Technology, Inc.
DECEMBER 2002
DSC 5618/5
1
Functional Block Diagram
Features:
x
256K x 36 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
– 64 independent 4K x 36 banks
– 9 megabits of memory on chip
x
Bank access controlled via bank address pins
x
High-speed data access
– Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns
(133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
x
Selectable Pipelined or Flow-Through output mode
x
Counter enable and repeat features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
x
Separate byte controls for multiplexed bus and bus
matching compatibility
x
LVTTL- compatible, 3.3V (±150mV) power supply
for core
x
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
x
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
x
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
x
Supports JTAG features compliant with IEEE 1149.1
HIGH-SPEED 3.3V 256K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S
4Kx36
MEMORY
ARRAY
(BANK 63)
MUX
PL/
FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/
WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
I/O0L-35L
A11L
A0L
JTAG
4Kx36
MEMORY
ARRAY
(BANK 1)
MUX
4Kx36
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
I/O0R-35R
A11R
A0R
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
5618 drw 01
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
,
PL/
FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/
WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
TMS
TCK
TRST
TDI
TDO
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
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