參數(shù)資料
型號(hào)： IDT5T9010BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144
封裝： PLASTIC, BGA-144
文件頁(yè)數(shù)： 22/23頁(yè)
文件大?。?/td> 168K
代理商： IDT5T9010BBI
8
INDUSTRIALTEMPERATURERANGE
IDT5T9010
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1)
Symbol
Parameter
Test Conditions
Min.
Typ.(7)
Max
Unit
Input Characteristics
IIH
Input HIGH Current
VDD = 2.7V
VI = VDDQ/GND
—
±5
μA
IIL
Input LOW Current
VDD = 2.7V
VI = GND/VDDQ
——
±5
VIK
Clamp Diode Voltage
VDD = 2.3V, IIN = -18mA
—
- 0.7
- 1.2
V
VIN
DC Input Voltage
- 0.3
+3.6
V
VDIF
DC Differential Voltage(2,8)
0.2
—
V
VCM
DC Common Mode Input Voltage(3,8)
680
750
900
mV
VIH
DC Input HIGH(4,5,8)
VREF + 100
—
mV
VIL
DC Input LOW(4,6,8)
—VREF - 100
mV
VREF
Single-EndedReferenceVoltage(4,8)
—
750
—
mV
Output Characteristics
VOH
Output HIGH Voltage
IOH = -8mA
VDDQ - 0.4
—
V
IOH = -100
μAVDDQ - 0.1
—
VOL
Output LOW Voltage
IOL = 8mA
—
0.4
V
IOL = 100
μA
—
0.1
VOX
FB/
FB Output Crossing Point
VDDQ/2 - 150
VDDQ/2
VDDQ/2 + 150
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode,
REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS(1)
Symbol
Parameter
Test Conditions(2)
Typ.
Max
Unit
IDDQ
Quiescent VDD Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
100
150
mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,
FBF[2:0] = LHH, Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current(3)
VDDQ = Max., REF = LOW,
PD = HIGH, nSOE = LOW,
0.75
50
μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:0] = LHH,
FBF[2:0] = LHH, Outputs enabled, All outputs unloaded
IDDPD
Power Down Current
VDD = Max.,
PD = LOW, nSOE = LOW, PLL_EN = HIGH
1.7
5
mA
IDDD
Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
18
30
μA/MHz
CurrentperOutput
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
19
30
μA/MHz
CurrentperOutput
ITOT
Total Power VDD Supply Current(4)
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF
115
170
mA
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF
145
220
ITOTQ
Total Power VDDQ Supply Current(4)
VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF
50
75
mA
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF
150
225
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4. FS = HIGH.
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