參數(shù)資料
型號(hào)： IDT49C465PQF8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 算術(shù)邏輯單元
英文描述： 49C SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 39/39頁(yè)
文件大小： 299K
代理商： IDT49C465PQF8
9
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DIAGNOSTIC FEATURES — DETAILED DESCRIPTION
Mode 2-0
x11
“NORMAL” Mode
In this mode, operation is “Normal” or non-diagnostic.
x10
“GENERATE-DETECT” Mode
When the EDC unit is in the “Generate-Detect” Mode, data is not corrected or altered by the error correction network. (Also referred to as
the “Detect-only” mode.)
000
“ERROR-DATA-OUTPUT” Mode
In this mode, the 32-bit data from the Error-Data Register is output on the SD bus.
Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register if the error counter
contents indicates “0” and there is a positive transition on the SYNCLK input when the ERR signal is LOW. Thus, the Error-Data Register
contains memory data corresponding to the first error to occur since the register was cleared. This register is cleared by pulling the CLEAR
input LOW. The register is read by the System Data bus by entering the “Error-Data-Output” Mode and enabling the System Data bus
output drivers.
All-Zero-Data: The Error-Data Register can be used as an “all-zero-data” source for memory initialization in systems where the initialization
process is to be done entirely by hardware.
x01
“DIAGNOSTIC-OUTPUT” Mode
In this mode, data from the diagnostic registers, the PCBI bus, and the CBI bus is output on the SD bus.
Direct Checkbit Readback: Internal data paths allow both the “Partial-Checkbit-Input” bus and the data in the “Checkbit-Input” latch to be
read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial Checkbit Input Bus are read via the
System bus by entering the “Diagnostic-Output” Mode and enabling the System Data bus output drivers. The checkbits are output on the
System Data bus bits 0-7; the Partial Checkbits are output on bits 8-15.
Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal Syndrome Register if the
error counter contents indicates “0” and there is a positive transition on the SYNCLK input when the ERR signal is LOW. This register is
cleared by pulling the CLEAR input LOW. The register is read by the System Data bus by entering the “Diagnostic-Output” Mode and
enabling the System Data bus output drivers. This data is output on SD bits 16-23.
Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which corresponds to a
count of 15, and there is a positive transition on the SYNCLK input where the ERR signal is LOW. This counter is cleared by pulling the
CLEAR input LOW. The counter is read by the System Data bus by entering the “Diagnostic-Output” Mode and enabling the System Data
bus output drivers. The data is output on SD bits 24-27.
Test Register: These two bits are reserved for factory diagnostics only and must not be used by system software. This data is output on
System Data bus bits 28-29.
Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves two bits which indicate whether a recorded error was a
single or a multiple-bit error. This register holds only the first error type to occurs after the last Clear operation. This data is output on
System Data bus bits 30-31.
100
Direct Read-Path Checkbit Injection: In the “Checkbit-Injection” Mode, bits 0-7 of the System Data input latch are presented to the
inputs of the Checkbit Input Latch. If MLE is strobed, the checkbit latch will be loaded with this value in place of the checkbits from memory.
By inserting various checkbit values, operation of the correction function of the EDC can be verified “on-board”. Except for the “Checkbit-
Injection” function, operation in this mode is identical to “Normal” Mode operation.
DIAGNOSTIC DATA FORMAT (SYSTEM BUS)
Latched Data
Error
Type
Re-
served
Error Counter
Syndrome Bits
Byte 3
Byte 2
SM
-
23 22 21
20
765
432
10
31 30
27
24 23
16
Data Out (Unlatched)
Partial Checkbits
Checkbits
Byte 1
Byte 0
765432
1
0
7
6
5
4
32
1
0
15
8
7
0
相關(guān)PDF資料
PDF描述
IDT49FCT818AEB 8-BIT, DSP-PIPELINE REGISTER, CDFP24
IDT49FCT818P 8-BIT, DSP-PIPELINE REGISTER, PDIP24
IDT49FCT818L 8-BIT, DSP-PIPELINE REGISTER, CQCC28
IDT49FCT818LB 8-BIT, DSP-PIPELINE REGISTER, CQCC28
IDT49FCT818PB 8-BIT, DSP-PIPELINE REGISTER, PDIP24
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IDT49C466APQF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
IDT49C466GB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Error Detection & Correction (EDAC)
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