參數(shù)資料
型號: IDT49C465PQF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 算術邏輯單元
英文描述: 49C SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQFP144
封裝: PLASTIC, QFP-144
文件頁數(shù): 32/39頁
文件大小: 299K
代理商: IDT49C465PQF8
38
COMMERCIAL TEMPERATURE RANGE
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
Pulse
Generator
R T
D.U.T.
V CC
V IN
C L
V OUT
50pF
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW-HIGH
PULSE
LOW -HIGH-LOW
PULSE
tW
1.5V
SAME PHA SE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SW ITCH
CLOSE D
SWITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
TEST WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
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