參數(shù)資料
型號(hào): IDT49C465PQF8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 算術(shù)邏輯單元
英文描述: 49C SERIES, 32-BIT ERROR DETECT AND CORRECT CKT, PQFP144
封裝: PLASTIC, QFP-144
文件頁數(shù): 30/39頁
文件大?。?/td> 299K
代理商: IDT49C465PQF8
36
COMMERCIAL TEMPERATURE RANGE
IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS—64-BIT CONFIGURATION
Figure 14. 64-Bit Single Chip "Generate Only" Timing
Parameter
Name
Propagation Delay
From
To
Min./
Max.
SDIN Set-up to SLEIN = Low
tSSLS
tSSLH
SDIN Hold to SLEIN = Low
min.
tSSLS
tSSLH
tSC
tS LC
SLE = H igh to CB O
(1)
max.
(1)
SLE
tS LC
(1)
tCECZx
CBOE = Low to CBO Enabled
CBOE
CBO
Final Checkbits Out
max.
SOE
MOE
MD Bus
ValidDAT AIN
SD Bus
to
1
2
3
4
5
ValidDAT AIN
to12
34
5
SINGLE
465
(MOE = Tied high)
(SO E = Tied high)
MDIN Set-up to M LEIN = Low
tMM LS
tMM LH
MDIN Hold to M LE IN = Low
min.
tMM LS
tMM LH
tM LC
MLEIN = High to CBO
(2)
max.
(2)
tMLC
(2)
MLE
tMC
tM C
Bits 32-63 to CBO
Bits 0-31 to CBO
max.
tCECZx
NOTES:
1. Assumes that System Data is valid at least 3ns before SLE goes HIGH.
2. Assumes that Memory Data is valid at least 4ns before MLE goes HIGH.
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