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參數(shù)資料
| 型號： | ICSSSTUF32866EHLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | GREEN, MO-205CC, LFBGA-96 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 310K |
| 代理商： | ICSSSTUF32866EHLFT |
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17
ICSSSTUF32866E
1038B—05/03/05
Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
pair; C0 = 1, C1 = 1; RST# being held high
PAR_IN is driven from PPO of the first SSTU32866 device
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
CK
D1D14
RST#
tsu
tpd
CK to PPO
th
tsu
th
tpdm , t pdmss
CK to Q
DCS#
CSR#
CK#
Q1Q14
PAR_IN
nn + 1
n + 2
PPO
n + 3
n + 4
QERR#
(not used)
tPHL or t PLH
CK to QERR#
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input event
Data to QERR#
Latency
Data to PPO
Latency
2. Device standard (cont'd)
2.7 Register timing (cont'd)
Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
pair; C0 = 1, C1 = 1; RST# being held high
PAR_IN is driven from PPO of the first SSTU32866 device
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
CK
D1D14
RST#
tsu
tpd
CK to PPO
th
tsu
th
tpdm , t pdmss
CK to Q
DCS#
CSR#
CK#
Q1Q14
PAR_IN
nn + 1
n + 2
PPO
n + 3
n + 4
QERR#
(not used)
tPHL or t PLH
CK to QERR#
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input event
Data to QERR#
Latency
Data to PPO
Latency
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