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參數(shù)資料
| 型號： | ICS952601yFLFT |
| 英文描述： | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| 中文描述： | 可編程定時控制中心⑩處理器的下一代小⑩ |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 181K |
| 代理商： | ICS952601YFLFT |
20
Integrated
Circuit
Systems, Inc.
ICS952601
0701G—10/13/04
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
CPU_Stop#
1.8mS
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
CPU_Stop#
1.8mS
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS952601YGLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| ICS952606 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952606FLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952607 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
| ICS952607YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor |
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