參數(shù)資料
型號(hào)： ICS952601yFLFT
英文描述： Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
中文描述： 可編程定時(shí)控制中心⑩處理器的下一代?、?/td>
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 181K
代理商： ICS952601YFLFT
14
Integrated
Circuit
Systems, Inc.
ICS952601
0701G—10/13/04
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI Stop Functionality
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The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
PCI_STOP#
Tsu
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# Assertion (transition from '1' to '0')
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
PCI_STOP#
Tsu
Tdrive_SRC
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS952601YGLFT 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
ICS952606 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952606FLFT 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952607 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952607YFLF-T 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
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