參數(shù)資料
型號(hào): ICS952601yFLFT
英文描述: Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
中文描述: 可編程定時(shí)控制中心⑩處理器的下一代小⑩
文件頁(yè)數(shù): 19/24頁(yè)
文件大?。?/td> 181K
代理商: ICS952601YFLFT
19
Integrated
Circuit
Systems, Inc.
ICS952601
0701G—10/13/04
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU Clock Tristate Timing
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
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ICS952601YGLFT 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
ICS952606 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
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ICS952607 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952607YFLF-T 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor