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參數(shù)資料
| 型號： | ICS9248YF-153-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 293K |
| 代理商： | ICS9248YF-153-T |
3
ICS9248-153
Third party brands and names are the property of their respective owners.
Notes:
1. Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
2. PWD = Power-Up Default
Byte 6: SDRAM Clock & Generator Mode Control Register
I
2C Command Bitmaps
Bit
PWD
7
0
00
0
133.33
33.33
66.67
00
0
1
95
31.67
63.33
00
0
1
0
100.99
33.66
67.33
00
0
1
115
38.33
76.67
00
1
0
100.7
33.57
67.13
00
1
0
1
103
34.33
68.67
00
1
0
105
35.00
70.00
00
1
110
36.67
73.33
01
0
102
34.00
68.00
01
0
1
104
34.67
69.33
01
0
1
0
106
35.33
70.67
01
0
1
107
35.67
71.33
01
1
0
108
36.00
72.00
01
1
0
1
109
36.33
72.67
01
1
0
90
30.00
60.00
01
1
111
37.00
74.00
10
0
112
37.33
74.67
10
0
1
113
37.67
75.33
10
0
1
0
114
38.00
76.00
10
0
1
116
38.67
77.33
10
1
0
117
39.00
78.00
10
1
0
1
118
39.33
78.67
10
1
0
119
39.67
79.33
10
1
120
30.00
60.00
11
0
142
35.50
71.00
11
0
1
144
36.00
72.00
11
0
1
0
146
36.50
73.00
11
0
1
138
34.50
69.00
11
1
0
136
34.00
68.00
11
1
0
1
135
33.75
67.50
11
1
0
140
35.00
70.00
11
1
150
37.50
75.00
0
0 - SDRAM_OUT Disable
1 - SDRAM_OUT Enable
1
AGP
01000
Note1
1
0 - Frequency is selected by hardware select, latched input;
Spread controlled by pin 29
1 - Frequency is selected by Bit (6:2); Spread controlled by Bit 7
0
Description
Spread Spectrum enable (+/- 0.25% center spread) 0=OFF 1=ON
6:2
Bit 3
Bit 2
FS2
Bit 6
FS1
Bit 5
FS0
Bit 4
CPU,
SDRAM
PCI
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