參數(shù)資料
型號(hào): ICS9248YF-153-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, SSOP-48
文件頁(yè)數(shù): 3/14頁(yè)
文件大?。?/td> 293K
代理商: ICS9248YF-153-T
11
ICS9248-153
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-153 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a
system when used with a Zero Delay Buffer Chip such as the ICS9179-06.
Spread spectrum may be enabled through I
2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-153
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2C interface allows changing functions, stop clock programming and frequency selection.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-153. All other clocks will continue to run while the CPUCLKs clocks are
disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width
is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS9248-153.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCICLK
CPUCLKT
CPUCLKC
PD# (High)
CPU_STOP#
INTERNAL
CPUCLK
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