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參數(shù)資料
| 型號(hào)： | ICS9248YF-153-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 293K |
| 代理商： | ICS9248YF-153-T |
12
ICS9248-153
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-153. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-153 internally. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off
latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PWR_DWN#
PCICLK
(External)
PCI_STOP#
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