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參數(shù)資料
| 型號： | ICS1562BM-201T |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO CLK SYNTHESIZER 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器，時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，TTL，晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1562BM-201T |
BIT(S)
BIT REF.
DESCRIPTION
33-38
M[0]..M[5]
M counter control bits
Modulus = value +1
39
FBKPOL
External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of EXTFBK
when FBKPOL=0.
40
DBLFREQ
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
41-44
A[0]..A[3]
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
45
RESERVED
Set to zero.
46
LOADEN~
Load clock divider enable (active low). When set to logic 1, the LOAD
and LD/N2 outputs will cease toggling.
47
SKEW-
Differential output duty factor adjust.
48
SKEW+
49-55
R[0]..R[6]
Reference divider modulus control bits
Modulus = value + 1
56
REFPOL
PLL locks to the rising edge of XTAL1 input when REFPOL=1 and to
the falling edge of XTAL1 when REFPOL=0.
SKEW+
SKEW-
0
Default
0
1
Reduces THIGH by approximately
100 ps
1
0
Increases THIGH by approximately
100 ps
1
Do not use
ICS1562B
13
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