參數(shù)資料
型號: ICS1562BM-201T
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 19/20頁
文件大?。?/td> 0K
描述: IC VIDEO CLK SYNTHESIZER 16-SOIC
產(chǎn)品變化通告: Product Discontinuation 13/May/2009
標(biāo)準(zhǔn)包裝: 2,500
類型: 時鐘/頻率合成器,時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,TTL,晶體
輸出: CMOS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 1:3
差分 - 輸入:輸出: 無/是
頻率 - 最大: 260MHz
除法器/乘法器: 是/是
電源電壓: 4.75 V ~ 5.25 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
其它名稱: 1562BM-201T
Register Mapping - ICS1562B-001 (Parallel Programming Option)
NOTE: IT IS NOT NECESSARY TO UNDERSTAND THE FUNCTION OF THESE BITS TO USE THE ICS1562B. PC SOFTWARE IS AVAILABLE
FROM ICS TO AUTOMATICALLY GENERATE ALL REGISTER VALUES BASED ON REQUIREMENTS. CONTACT FACTORY FOR DETAILS.
REG#
BIT(S)
BIT REF.
DESCRIPTION
0
0-3
R[0]..R[3]
Reference divider modulus control bits
1
0-2
R[4]..R[6]
Modulus = value + 1
1
3
REFPOL
PLL locks to the rising edge of XTAL1 input when REFPOL=1 and
to the falling edge of XTAL1 when REFPOL=0.
2
0-3
A[0]..A[3]
Controls A counter. When set to zero, modulus=7. Otherwise,
modulus=7 for “value” underflows of the prescaler, and modulus=6
thereafter until M counter underflows.
3
0-3
M[0]..M[3]
M counter control bits
4
0-1
M[4]..M[5]
Modulus = value + 1
4
2
FBKPOL
External feedback polarity control bit. The PLL will lock to the falling
edge of EXTFBK when FBKPOL=1 and to the rising edge of
EXTFBK when FBKPOL=0.
4
3
DBLFREQ
Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14).
5
0-3
N1[0]..N1[3]
Sets N1 modulus according to this table. These bits are set to imple-
ment a divide-by-four on power-up.
N1[3]
N1[2]
N1[1]
N1[0]
RATIO
00003
00014
00104
00115
01006
01018
01108
0111
10
1X
0
12
1X
0
1
16
1X
1
0
16
1X
1
20
X=Don’t Care
ICS1562B
8
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