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參數(shù)資料
| 型號(hào)： | ICS1562BM-201T |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO CLK SYNTHESIZER 16-SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器，時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，TTL，晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1562BM-201T |
BIT(S)
BIT REF.
DESCRIPTION
13-14
S[0]..S[1]
PLL post-scaler/test mode select bits.
S[1] S[0]
DESCRIPTION
0
Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
0
1
Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1
0
Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divder
drives the LOAD output which, in turn, drives the N2 divider.
1
AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
15
AUX_CLK
When in the AUXEN clock mode, this bit controls the differential outputs.
16
AUX_N1
When in the AUXEN clock mode, this bit controls the N1 output (and
consequently the N2 output according to its programming). When not in
the AUXEN clock mode, this bit, if set to one, will override the N1 divider
modulus and output the VCO frequency divided by two [F(PLL)/2] at the
LOAD output.
17-24
N2[0]..N2[7]
Sets the modulus of the N2 divider. The input of the N2 divider is the
28
N2[8]
output of the N1 divider in all clock modes except AUXEN.
25-27
V[0]..V[2]
Sets the gain of VCO according to this table.
V[2]
V[1]
V[0]
VCO GAIN
(MHz/VOLT)
100
30
101
45
110
60
111
80
29-30
P[0]..P[1]
Sets the gain of the phase detector according to this table.
P[1]
P[0]
GAIN (uA/radian)
00
0.05
01
0.15
10
0.5
11
1.5
31
RESERVED
Set to zero.
32
P[2]
Phase detector tuning bit. Should normally be set to one.
ICS1562B
12
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