參數(shù)資料
型號(hào)： IBM25PPC750L-GB375A2R
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 375 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 48/48頁(yè)
文件大?。?/td> 608K
代理商： IBM25PPC750L-GB375A2R
12/8/99
Version 1.02
Page 9
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Electrical and Thermal Characteristics
DC Electrical Characteristics
The 750 60x bus power supply can be either 3.3V, 2.5V, or 1.8V nominal; likewise, the L2 power supply can
be either 3.3V, 2.5V, or 1.8V nominal. See the pinout listing for more information
Absolute Maximum Ratings See Notes
Characteristic
Symbol
Value
Unit
Core supply voltage
V
DD
-0.3 to 2.5
V
PLL supply voltage
AV
DD
-0.3 to 2.5
V
L2 DLL supply voltage
L2AV
DD
-0.3 to 2.5
V
60x bus supply voltage
OV
DD(3.3V)
-0.3 to 3.6
V
OV
DD(2.5V)
-0.3 to 2.8
OV
DD(1.8V)
-0.3 to 2.1
L2 bus supply voltage
L2OV
DD
-0.3 to 3.6
V
Input voltage
V
IN(3.3V)
-0.3 to 3.6
V
IN(2.5V)
-0.3 to 2.8
V
IN(1.8V)
-0.3 to 2.1
Storage temperature range
T
STG
-55 to 150
°C
Note:
1. Functional and tested operating conditions are given in Table ”Recommended Operating Conditions,” below. Absolute maximum ratings are stress rat-
ings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. Caution: VIN must not exceed OVDD by more than 0.3V at any time, including during power-on reset. This is a DC specification only. VIN overshoot tran-
sients up to OVDD+1V, and undershoots down to GND-1V (both measured with the 740 in the circuit) are allowed for up to 5ns.
3. Caution: OVDD must not exceed VDD/AVDD by more than 2.0V at any time during normal operation. On power up and power down, OVDD is allowed to
exceed VDD/AVDD by up to 3.3V for up to 20 ms, or by up to 2.5V for 40 ms. Excursions beyond 40 ms or 3.3V are not allowed.
4. Caution: VDD/AVDD must not exceed OVDD by more than 0.4V during normal operation. On power up and power down, VDD/AVDD is allowed to exceed
OVDD by up to1.0V for up to 20 ms, or by up to 0.7V for 40 ms. Excursions beyond 40 ms or 1.0V are not allowed.
Recommended Operating Conditions
Characteristic
Symbol
Value
Unit
Notes
Core supply voltage
V
DD
2.0
V
1, 2
PLL supply voltage
AV
DD
V
DD
V1
L2DLL supply voltage
L2AV
DD
V
DD
V1
60x bus supply voltage, pin W1 tied high
OV
DD(3.3V)
3.135 to 3.465
V
1
60x bus supply voltage pin W1 tied to HRESET
OV
DD(2.5V)
2.375 to 2.625
V
1
60x bus supply voltage, pin W1 tied to GND
OV
DD(1.8V)
1.71 to 1.89
V
1
L2 bus supply voltage, pin A19 tied high
L2OV
DD(3.3V)
3.135 to 3.465
V
1
L2 bus supply voltage, pin A19 tied to HRESET
L2OV
DD(2.5V)
2.375 to 2.625
V
1
Note:
1. These are recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
2.
V
DD and TJ are specified by the Application Conditions designator in the part number. See the Part Number Key on Page 43 for more information.
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