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參數(shù)資料
| 型號： | IBM25PPC750L-EB0C375W |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 375 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 31/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | IBM25PPC750L-EB0C375W |
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9/30/99
Version 2.0
Datasheet
Page 33
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
Pull-up / Pull-down Resistor Requirements
The PID8p-750 requires high-resistive (weak: 10K
) pull-up resistors on several control signals of the bus
interface to maintain the control signals in the negated state after they have been actively negated and
released by the PID8p-750 or other bus masters. These signals are: TS, ABB, DBB, and ARTRY.
In addition, the PID8p-750 has one open-drain style output that requires a pull-up resistor (weak or stronger:
4.7K
- 1- K) if it is used by the system. This signal is: CKSTP_OUT.
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled. If all parity generation is disabled through HID0, than all
parity checking should also be disabled through HID0. It is still recommended that the unused address or
data parity signals be tied high through pull up resistors to minimize noise on the package.
No pull-up resistors are normally required for the L2 interface.
HRESET Requirements
HRESET needs to be actively driven.
Resistor Pull-up / Pull-down Requirements
Required or Recommended Actions
Signals
Strong pull-up required
CKSTP_OUT
Weak pull-up required
TLBISYNC, LSSD_MODE, L1_TSTCLK, L2_TSTCLK, TS, ABB, DBB,
ARTRY,
Weak pull-up or pull-down required
TCK
Weak pull-up recommended
SRESET, GBL, TBST,SMI, INT, MCP, CKSTP_IN
Weak pull-up recommended if pin not used
AP0-AP3, DP0-DP7
Note: See “PowerPC PID8p-750 Microprocessor Pinout Listings” section on page 24 for additional comments about these signals.
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