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參數(shù)資料
| 型號： | IBM25PPC750L-EB0C375W |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 375 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 21/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | IBM25PPC750L-EB0C375W |
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Page 24
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
PowerPC PID8p-750 Microprocessor Pinout Listings
The following table provides the pinout listing for the 360 CBGA package (the PID8p-750).
Pinout Listing for the 360 CBGA package5
Signal Name
Pin Number
Active
I/O
A0-A31
A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2,
L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2
High
I/O
AACK
N3
Low
Input
ABB
L7
Low
I/O
AP0-AP38
C4, C5, C6, C7
High
I/O
ARTRY
L6
Low
I/O
AVDD 9
A8
——
BG
H1
Low
Input
BR
E7
Low
Output
CKSTP_OUT
D7
Low
Output
CI
C2
Low
Output
CKSTP_IN
B8
Low
Input
CLKOUT
E3
--
Output
DBB
K5
Low
I/O
DBDIS
G1
Low
Input
DBG
K1
Low
Input
DBWO
D1
Low
Input
DH0-DH31
W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10,
W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3,
U4, R5
High
I/O
DL0-DL31
M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13,
W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3,
U3, W2
High
I/O
DP0-DP78
L1, P2, M2, V2, M1, N2, T3, R1
High
I/O
DRTRY
H6
Low
Input
GBL
B1
Low
I/O
Note:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
3. Internally tied to L2OVDD in the PID8p-750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. Pull up and pull down resistor requirements for all pins are listed in the “Pull-up / Pull-down Resistor Requirements” section on page 33
6. BVSEL selects the I/O voltage on the 60X bus. L2VSEL selects the I/O voltage on the L2 bus. Please refer to the Table “Recommended Operating
Conditions1,2,3,” on page 6, for the use of these pins.
7. TCK must be tied high or low for normal machine operation.
8. Address and data parity signals must be tied high or low if unused in the design.
9. Starting with rev levels dd3.X, the AVDD pin is no longer brought out to the package.
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