參數(shù)資料
型號(hào)： IBM25PPC750L-EB0C375W
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 375 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 24/46頁(yè)
文件大?。?/td> 610K
代理商： IBM25PPC750L-EB0C375W
Page 26
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
PLL_CFG[0-3]
A4, A5, A6, A7
High
Input
QACK
B2
Low
Input
QREQ
J3
Low
Output
RSRV
D3
Low
Output
SMI
A12
Low
Input
SRESET
E10
Low
Input
SYSCLK
H9
—
Input
TA
F1
Low
Input
TBEN
A2
High
Input
TBST
A11
Low
I/O
TCK7
B10
High
Input
TDI
B7
High
Input
TDO
D9
High
Output
TEA
J1
Low
Input
TLBISYNC
A3
Low
Input
TMS
C8
High
Input
TRST
A10
Low
Input
TS
K7
Low
I/O
TSIZ0-TSIZ2
A9, B9, C9
High
Output
TT0-TT4
C10, D11, B12, C12, F11
High
I/O
WT
C3
Low
Output
VDD 2
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
—
VOLTDET3
K13
High
Output
BVSEL6
W1
—
Input
L2VSEL6
A19
—
Input
Pinout Listing for the 360 CBGA package5
Signal Name
Pin Number
Active
I/O
Note:
1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core.
3. Internally tied to L2OVDD in the PID8p-750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. Pull up and pull down resistor requirements for all pins are listed in the “Pull-up / Pull-down Resistor Requirements” section on page 33
6. BVSEL selects the I/O voltage on the 60X bus. L2VSEL selects the I/O voltage on the L2 bus. Please refer to the Table “Recommended Operating
Conditions1,2,3,” on page 6, for the use of these pins.
7. TCK must be tied high or low for normal machine operation.
8. Address and data parity signals must be tied high or low if unused in the design.
9. Starting with rev levels dd3.X, the AVDD pin is no longer brought out to the package.
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