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參數(shù)資料
| 型號： | IBM25PPC405GPR3DB400Z |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 27 X 27 MM, ENHANCED, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 58/58頁 |
| 文件大?。?/td> | 1264K |
| 代理商： | IBM25PPC405GPR3DB400Z |
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Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
3/14/03
Page 9 of 58
- PCI interrupt acknowledge
- PCI special cycle
Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four physical banks. Up
to 256MB per bank are supported, up to a maximum of 1 GB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
32-bit memory interface support
Programmable address compare for each bank of memory
Industry standard 168-pin DIMMS are supported (some configurations)
All PPC405GPrs support up to 133 MHz memory with PC-133 support
4MB to 256 MB per bank
Programmable address mapping and timing
Auto refresh
Page mode accesses with up to 4 open pages
Power management (self-refresh)
Error checking and correction (ECC) support
- Standard single-error correct, double-error detect coverage
- Aligned nibble error detect
- Address error logging
External Peripheral Bus Controller (EBC)
Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
Up to 66 MHz operation
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus width support
Latch data on Ready
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