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參數(shù)資料
| 型號： | IBM25PPC405GPR3DB400Z |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 27 X 27 MM, ENHANCED, PLASTIC, BGA-456 |
| 文件頁數(shù)： | 52/58頁 |
| 文件大?。?/td> | 1264K |
| 代理商： | IBM25PPC405GPR3DB400Z |
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Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
Page 56 of 58
3/14/03
Revision Log
ROM Location
U2
HoldAck
PPC405GPr Peripheral Attach
0
PPC405GPr PCI Attach
1
PCI Asynchronous Mode
Enable
Y3
ExtAck
Synchronous PCI Mode
0
Asynchronous Mode
1
External Bus Synchronous
Mode Enable 3
A22
GPIO3[TS1O]
Asynchronous Mode
0
Synchronous Mode
1
PCI Arbiter Enable 3
AF18
GPIO4[TS2O]
Internal Arbiter Disabled
0
Internal Arbiter Enabled
1
New Mode Enable
In Legacy mode the
PPC405GPr functions like the
PPC405GP.
If not strapped, the
PPC405GPr defaults to
Legacy mode.
D20
GPIO24
Legacy (PPC405GP) mode
0
New (PPC405GPr) mode4
1
Flip Circuit Disable
(must be strapped low (0)
during initilization).
AB3
GPIO9[TrcClk]
Normal operation0
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances
such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr,
visit the technical documents area of the IBM PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in
“Clocking Specifications” on page 43. Further requirements are detailed in the Clocking chapter of the
PowerPC 405GPr
Embedded Processor User’s Manual.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by
using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
4. The pull-up initialization strapping resistor must be 1 k
rather than 3k in order to overcome the internal pull-down resistor.
Date
Contents of Modification
03/13/2003
400 MHz part numbers and new power/current numbers
PPC405GPr New Mode Strapping Pin Assignments (Part 3 of 3)
Function
Option
Ball Strapping
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