參數(shù)資料
型號(hào)： IBM25NPE405H-3BA266CZ
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA580
封裝： 35 MM, PLASTIC, EBGA-580
文件頁(yè)數(shù)： 43/74頁(yè)
文件大小： 1423K
代理商： IBM25NPE405H-3BA266CZ
Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
48
SDRAM Interface
MemAddr00:31
Memory Data bus
Notes:
1. MemAddr00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:00
Memory Address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
O3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lane 0 (MemAddr00:7),
1 (MemAddr08:15),
2 (MemData16:23), and
3 (MemData24:31)
O3.3V LVTTL
DQMCB
DQM for ECC check bits.
O
3.3V LVTTL
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
BankSel0:3
Select up to four external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases,
glueless SDRAM attachment without requiring this signal
to be repowered by a PLL or zero-delay buffer.
O3.3V LVTTL
External Slave Peripheral Bus Interface
PerData00:31
External peripheral data bus when not in external master
mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this
bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr00:31
External peripheral address bus when not in external
master mode, otherwise used by external master.
I/O
5V tolerant
3.3V LVTTL
1
PerPar0:3
External peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:3
Peripheral write-bte enable. Byte-enables which are valid
for an entire cycle or write-byte-enables which are valid for
each byte on each data transfer, allowing partial word
transactions. Used by either external bus controller or DMA
controller depending upon the type of transfer involved.
Used as inputs when external bus master owns the
external interface.
I/O
5V tolerant
3.3V LVTTL
1, 2, 7
Signal Functional Description (Part 5 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 43.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
IBM25NPE405H-3DA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA580
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