參數(shù)資料
型號(hào)： IBM13Q16734HCB
廠商： IBM Microeletronics
英文描述： 16M x 72 Registered SDRAM Module(16M x 72 200腳寄存同步動(dòng)態(tài)RAM模塊)
中文描述： 16米x 72注冊(cè)內(nèi)存模塊（16米x 72 200腳寄存同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 6/14頁(yè)
文件大?。?/td> 275K
代理商： IBM13Q16734HCB
IBM13Q16734HCB
16M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 14
04K8915.C75644E
6/00
Output Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V to 3.6V)
Symbol
Parameter
Min.
Max.
Units
I
I(L)
Input Leakage Current, any input
(0.0V
≤
V
IN
≤
3.6V), All Other Pins Not Under Test = 0V
-20
+20
μ
A
I
O(L)
Output Leakage Current (DQ)
(D
OUT
is disabled, 0.0V
≤
V
OUT
≤
3.6V)
-2
+2
μ
A
V
OH
Output Level (TTL)
Output “H” Level Voltage (I
OUT
= -2.0mA)
2.4
V
DD
V
V
OL
Output Level (TTL)
Output “L” Level Voltage (I
OUT
= +2.0mA)
0.0
0.4
V
I
O(L)
Output Leakage Current (PD1 - PD8)
-10
+10
μ
A
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V to 3.6V)
Parameter
Symbol
Test Condition
Value
Units
Notes
Operating Current
I
CC1
1 bank operation
t
RC
= t
RC
(min), t
CK
= min
Active-Precharge command cycling
without burst operation
1311
mA
1, 3, 4
Precharge Standby Current in Power Down Mode
I
CC2P
CKE
≤
V
IL
(max), t
CK
= min, CS =V
IH
(min)
339
mA
2
I
CC2PS
CKE
≤
V
IL
(max), t
CK
= Infinity, CS =V
IH
(min)
43
mA
2
Precharge Standby Current in Non-Power Down Mode
I
CC2N
CKE
≥
V
IH
(min), t
CK
= min, CS =V
IH
(min)
771
mA
2, 5
I
CC2NS
CKE
≥
V
IH
(min), t
CK
= Infinity,
133
mA
2, 6
No Operating Current (Active state: 4 bank)
I
CC3N
CKE
≥
V
IH
(min), t
CK
= min, CS =V
IH
(min)
860
mA
2, 5
I
CC3P
CKE
≤
V
IL
(max), t
CK
= min,
447
mA
2, 7
Operating Current (Burst Mode)
I
CC4
t
CK
= min, Read/ Write command cycling,
Multiple banks active, gapless data,BL=4
1941
mA
1, 4, 8
Auto (CBR) Refresh Current
I
CC5
t
CK
= min, t
RC
= t
RC
(min)
CBR command cycling
2301
mA
1
Self Refresh Current
I
CC6
CKE
≤
0.2V
43
mA
2, 8
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (I
CC3N
).
2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed up to three times during t
RC
(min).
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during t
CK(min)
.
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