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參數(shù)資料
| 型號： | IBM13Q32734BCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Registered SDRAM Module(32M x 72 200腳寄存同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置注冊內(nèi)存模塊（32M × 72配置200腳寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 247K |
| 代理商： | IBM13Q32734BCA |
IBM13Q32734BCA
32M x 72 Registered SDRAM Module
04K8918.C75665B
6/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 15
Features
200-Pin JEDEC Standard, Registered 8-Byte
Dual In-line Memory Module
32M x 72 Synchronous DRAM DIMM
Performance:
Inputs and outputs are LVTTL (3.3V) compatible
Single 3.3V to 3.6V Power Supply
Single Pulsed RAS interface
Fully Synchronous to positive Clock Edge
Data Mask control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Programmable Operation:
-SDRAM CAS Latency: 2
-Burst Type: Sequential or Interleave
-Burst Length: 2
-Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Suspend Mode and Power Down Mode
12/10/2 Addressing (Row/Column/Bank)
4096 Refresh cycles distributed across 64ms
Parallel Presence Detect
Card size: 6.05" x 1.50" x 0.320"
Gold contacts
SDRAM
S
in TSOJ Type II, 2-High, Stacked
Package
Description
IBM13Q32734BCA is a registered 200-pin Synchro-
nous DRAM Dual In-line Memory Module (DIMM)
which is organized as a 32Mx72 high-speed mem-
ory array. The DIMM uses eighteen x4 SDRAMs in
400mil TSOJ II stacked packages. The DIMM
achieves high speed data transfer rates of up to
66MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
The DIMM is intended to comply with all non-
optional JEDEC standards set for the 200-pin regis-
tered SDRAM DIMMs.
All control and address signals are synchronized
with the positive edge of an externally supplied
clock. They are latched in an on-DIMM pipeline
register and presented to the SDRAMs on the fol-
lowing clock.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A13 using the Mode Register Set cycle.
The DIMM uses parallel presence detects imple-
mented according to the JEDEC standard.
All IBM 200-pin DIMMs provide a high performance,
flexible 8-byte interface in a 6.05” long high-perfor-
mance footprint. Related products include both EDO
DRAM and SDRAM unbuffered DIMMs in both non-
parity x64 and ECC-Optimized x72 configurations in
the 168 pin form factor.
CAS Latency = 2*
Clock Frequency
Clock Cycle
Clock Access Time
* SDRAM CAS latency = 2; DIMM CAS Latency = 3
-10
66
15
11.3
Units
MHz
ns
ns
f
CK
t
CK2
t
AC2
.
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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