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參數(shù)資料
| 型號： | IBM13M32734BCE |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置2，銀行注冊/緩沖內(nèi)存模組（32M × 72配置2組寄存/緩沖同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 328K |
| 代理商： | IBM13M32734BCE |
IBM13M32734BCE
32M x 72 2-Bank Registered/Buffered SDRAM Module
19L7293.E93875A
8/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 21
Clock Wiring
10 Ohm
CK0
Clock Net Wiring (CK0):
IN
SDRAM STACK
(2 DEVICES)
REG1 (1:1)
SDRAM STACK
(2 DEVICES)
One of 9 SDRAM outputs shown.
All PLL clock SDRAM loads equal.
Achieved in part through equal length
wiring.
FDBK
IN
(PLL out to Feedback input)
10 0hms
CK1, CK2, and CK3
Terminated Clock Nets (CK1, CK2, and CK3):
PCK
(2 SDRAM stack modules,
4 device loads per output)
OUT1
12pf
TO
OUT9
OUT11
12pf
Phase
Lock
Loop
1. The PLL is programmed via a combination
of the feedback path and on DIMM load-
ing. PLL feedback produces zero phase
shift from the delayed CK0 input.
2. Card wiring and capacitance loading varia-
tion:
±
100ps.
3. Timing is based on a driver with a 1 Volt/ns
rise time.
4. Feedback capacitor valve determined by
PLL phase characteristics.
Notes:
REG2 (1:1)
REG3 (1:1)
OUT10
8pf
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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