參數(shù)資料
型號(hào)： IBM13M32734BCE
廠商： IBM Microeletronics
英文描述： 32M x 72 2-Bank Registered/Buffered SDRAM Module(32M x 72 2組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 32M × 72配置2，銀行注冊(cè)/緩沖內(nèi)存模組（32M × 72配置2組寄存/緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 18/21頁(yè)
文件大小： 328K
代理商： IBM13M32734BCE
IBM13M32734BCE
32M x 72 2-Bank Registered/Buffered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 18 of 21
19L7293.E93875A
8/99
Functional Description and Timing Diagrams
Refer to IBM 168-pin SDRAM Registered DIMM Functional Description and Timing Diagrams (Document
01L5868.E24564) for Registered mode operation.
Refer to the IBM 64Mb Synchronous DRAM Die Revision C datasheet (Document 19L3265.E35856) for the
functional description and timing diagrams for Buffered mode operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
Presence Detect Read and Write Cycle
Symbol
f
SCL
T
I
t
AA
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
r
t
f
t
SU:STO
t
DH
t
WR
Parameter
Min.
Max.
Units
Notes
SCL Clock Frequency
100
KHz
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
Start Condition Hold Time
4.0
μ
s
Clock Low Period
4.7
μ
s
Clock High Period
4.0
μ
s
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
Data in Hold Time
0
μ
s
Data in Setup Time
250
ns
SDA and SCL Rise Time
1
μ
s
SDA and SCL Fall Time
300
ns
Stop Condition Setup Time
4.7
μ
s
Data Out Hold Time
300
ns
Write Cycle Time
15
ms
1
1. The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
相關(guān)PDF資料
PDF描述
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IBM13M32734CCB 32M x 72 1-Bank Registered / Buffered SDRAM Module(32M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
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IBM13M64734BCA 64M x 72 1 Bank Registered/Buffered SDRAM Module(64M x 72 1組寄存/緩沖同步動(dòng)態(tài)RAM模塊)
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