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| 型號： | IBM0164165P |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 16 13/9 EDO DRAM(4M x 16 動態(tài)RAM（超頁面模式讀寫并帶22條地址線，其中13條為行地址選通，9條為列地址選通）) |
| 中文描述： | 4米× 16 13 / 9 EDO公司的DRAM（4米× 16動態(tài)隨機存儲器（超頁面模式讀寫并帶22條地址線，其中13條為行地址選通，9條為列地址選通）） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 480K |
| 代理商： | IBM0164165P |
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IBM0164165B
IBM0164165P
4M x 16 13/9 EDO DRAM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 28
88H2012
GA14-4251-02
Revised 11/97
AC Characteristics
(T
A
=0 to +70
°
C, V
CC
=3.3
±
0.3V)
1. An initial pause of 100
μ
s is required after power-up followed by 8 RAS only refresh cycles before proper device operation is
achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh
cycles is required.
2. AC measurements assume t
T
=2ns.
3. V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V
IH
and V
IL
.
4. Valid column addresses are only A0 through A8.
Read, Write, Read-Modify-Write and Refresh Cycle
(Common Parameters)
Symbol
Parameter
-50
-60
Units
Notes
Min.
Max.
Min.
Max.
t
RC
Random Read or Write Cycle Time
84
—
104
—
ns
1
t
RP
RAS Precharge Time
30
—
40
—
ns
t
CP
CAS Precharge Time
8
—
10
—
ns
t
RAS
RAS Pulse Width
50
100k
60
100k
ns
1
t
CAS
CAS Pulse Width
8
100k
10
100k
ns
1
t
ASR
Row Address Setup Time
0
—
0
—
ns
t
RAH
Row Address Hold Time
7
—
10
—
ns
t
ASC
Column Address Setup Time
0
—
0
—
ns
t
CAH
Column Address Hold Time
7
—
10
—
ns
t
RCD
RAS to CAS Delay Time
11
37
14
45
ns
2
t
RAD
RAS to Col. Address Delay Time
9
25
12
30
ns
3
t
RSH
RAS Hold Time
8
—
10
—
ns
t
CSH
CAS Hold Time
40
—
50
—
ns
1
t
CRP
CAS to RAS Precharge Time
5
—
5
—
ns
1
t
DZO
OE Delay Time From D
IN
0
—
0
—
ns
4
t
DZC
CAS Delay Time From D
IN
0
—
0
—
ns
4
t
T
Transition Time (Rise and Fall)
1
50
1
50
ns
5
1. In a Test Mode Read cycle, the value of t
RAC
, t
AA
, t
CAC
and t
CPA
are delayed by 5ns from the specified value. These parameters
must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated timings must also be adjusted by 5ns.
2. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(max.) limit, then access time is controlled by t
CAC
.
3. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference point only. If t
RAD
is
greater than the specified t
RAD
(max.) limit, then access time is controlled by t
AA
.
4. Either t
DZC
or t
DZO
must be satisfied.
5. AC measurements assume t
T = 2ns.
Discontinued (8/98 - last order; 12/98 last ship)
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