參數(shù)資料
型號： IA8X44
廠商： Innovasic Semiconductor
英文描述： SDLC COMMUNICATIONS CONTROLLER
中文描述： SDLC的通信控制器
文件頁數(shù)： 24/49頁
文件大?。?/td> 220K
代理商： IA8X44
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER
Interrupts
The IA8044/IA8344 provides 5 interrupt sources. There are 2 external interrupts accessible
through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are,
also, internal interrupts associated with Timer 0 and Timer 1, and an internal interrupt from
the SIU.
External Interrupts
The choice between external interrupt level or transition activity is made by setting IT1
and IT0 bits in the Special Function Register TCON.
When the interrupt event happens, a corresponding Interrupt Control Bit is set (IT0 or
IT1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled.
When the interrupt service routine is vectored, the corresponding control bit (IT0 or IT1)
is cleared provided that the edge triggered mode was selected. If level mode is active, the
external requesting source controls flags IT0 or IT1 by the logic level on pins INT0 or INT1
(0 or 1).
Timer0 and Timer 1 Interrupts
Timer 0 and 1 interrupts are generated by TF0 and TF1 flags, which are set by the
rollover of Timer 0 and 1, respectively. When an interrupt is generated, the flag that caused
this interrupt is cleared by the hardware, if the CPU accessed the corresponding interrupt
service vector. This can be done only if this interrupt is enabled in the IE register.
Serial Interface Unit Interrupt
The SIU generates an interrupt when a frame is received or transmitted. No interrupts are generated
for a received frame with errors.
Interrupt Priority Level Structure
There are two priority levels in the IA8044/IA8344, and any interrupt can be individually
programmed to a high or low priority level. Modifying the appropriate bits in the Special
Function Register IP can accomplish this. A low priority interrupt service routine will be
interrupted by a high priority interrupt. However, the high priority interrupt can not be
interrupted.
If two interrupts of the same priority level occur, an internal polling sequence determines
which of them will be processed first. This polling sequence is a second priority structure
defined as follows:
IE0 1 – highest
TF0 2
IE1 3
TF1 4
SIU – lowest
Copyright
2003
innov
ASIC
The End of Obsolescence
ENG210010112-00
www.innovasic.com
Customer Support:
Page 24 of 49
1-888-824-4184
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