參數(shù)資料
型號： IA8X44
廠商： Innovasic Semiconductor
英文描述： SDLC COMMUNICATIONS CONTROLLER
中文描述： SDLC的通信控制器
文件頁數(shù)： 16/49頁
文件大?。?/td> 220K
代理商： IA8X44
IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER
Timers/Counters
Timers 0 and 1
The IA8X44 has two 16-bit timer/counter registers: Timer 0 and Timer 1. Both can be configured
for counter or timer operations. In timer mode, the register is incremented every machine cycle,
which means that it counts up after every 12 oscillator periods. In counter mode, the register is
incremented when the falling edge is observed at the corresponding input pin T0 or T1. Since it
takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/24 of the
oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper
recognition of 0 or 1 state, an input should be stable for at least 1 machine cycle (12 clock periods).
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function
Registers (TMOD and TCON) are used to select the appropriate mode.
Mode 0
In mode 0 the timers operate as an 8-bit timer (TH0/1) with a divide by 32 bit prescalar (TL0/1).
Mode 0 uses all 8 bits of TH0/1 and the lower 5 bits of TL0/1. The upper 3 bits of TL0/1 are
unknowns. Setting TR0/1 does not reset the registers TH0/1 and TL0/1. As the timer rolls over
from all 1’s to all 0’s it will set the interrupt flag TF0/1.
Mode 1
Mode 1 is the same as mode 0 except that all 8 bits of TL0/1 are used instead of just the lower 5
bits.
Mode 2
Mode 2 configures TL0/1 as an 8-bit counter with automatic reload from the contents of TH0/1.
Overflow of TL0/1 causes the interrupt TF0/1 to be set and the reload to occur. The contents of
TH0/1 are not affected by the reload.
Mode 3
Mode 3 creates two separate 8 bit counters from TL0 and TH0. TL0 uses the timer 0 mode bits
from TMOD, TMOD .0 through TMOD.3. TH0 is a timer only (not a counter) and uses timer 1’s
control bits, TR1 and TF1 for operation. Timer 1 can still be used if an interrupt is not required by
switching it in and out of its own mode 3. With TMOD.4 and TMOD.5 both high timer 1 will stop
and hold its count.
Timer Mode (TMOD):
The Timer Mode register contains bits that select the mode that the timers are to be operated in.
The lower nibble controls timer 0 and the upper nibble controls timer 1.
TMOD
Bit: 7
6
5
4
GATE
C/T
M1
M0
TMOD.0
M0
Timer 0 mode selector bit.
Copyright
2003
innov
ASIC
The End of Obsolescence
ENG210010112-00
www.innovasic.com
Customer Support:
Page 16 of 49
1-888-824-4184
3
2
1
0
GATE
C/T
M1
M0
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